Ssi Option Register; Table 30-21 Ssi Option Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Synchronous Serial Interface (SSI)

30.3.13 SSI Option Register

The SSI Option Register (SOR) allows the user to clear out the receive FIFO and/or the transmit FIFO,
turn the clock off when the SSI is disabled, and reset the frame synchronization and the state machine. This
register also includes a user-programmable field to set wait states.
SOR
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–7
CLKOFF Clock Off—Turns off the clocks when the SSI is disabled to further
Bit 6 reduce power consumption.
RX_CLR Receiver Clear—Controls whether the receive FIFO is flushed. The
Bit 5 transmit portion of the SSI is not affected. The software must clear
RX_CLR before the SSI transmitter can operate.
TX_CLR Transmitter Clear—Controls whether the transmit FIFO is flushed. The
Bit 4 receiver portion of the SSI is not affected. The software must clear
TX_CLR before the SSI transmitter can operate.
Reserved Reserved—These bits are reserved and should read 0.
Bits 3–1
SYNRST Frame Sync Reset—Resets the accumulation of data in the SRX register
Bit 0 and receive FIFO (RXFIFO) on frame synchronization.
30-34
SSI Option Register
28 27 26 25 24
r r r r
0 0 0 0 0
12 11 10 9 8
r r r r
0 0 0 0 0
Table 30-21. SSI Option Register Description
Description
MC9328MX1 Reference Manual
23 22 21
r r r r
0 0 0
0x0000
7 6 5
CLK
RX_CLR TX_CLR
OFF
r r rw rw
0 0 0
0x0000
Addr
0x00218028
20 19 18 17
r r r r
0 0 0 0
4 3 2 1
rw r r r
0 0 0 0
Settings
0 = Clocks enabled
when SSI disabled
1 = Clocks disabled
when SSI disabled
0 = No effect
1 = Clear receive FIFO
0 = No effect
1 = Clear transmit FIFO
0 = No effect
1 = Reset data
accumulation
MOTOROLA
16
r
0
0
SYN
RST
rw
0