Syncflash Program Mode; Figure 24-23 Load Command Register Timing Diagram; Figure 24-24 Syncflash Program Mode State Diagram - Motorola DragonBall MC9328MX1 Reference Manual

The activate and read comprise the final two commands in the triplet and must refer to the same bank as
the original command register load. Changes to the bank address within the triplet will return
indeterminate results. Details on command register encodings and operation are covered in Section 24.9.4,
"SyncFlash Configuration."
SDCLK
ADDR
RAS,
CAS,
SDWE
CSDx
DATA
Figure 24-23. Load Command Register Timing Diagram

24.6.7 SyncFlash Program Mode

SyncFlash programming and status checking operations require the same 3 command sequence described
in Section 24.6.6. Because these operations are repeated many thousands of times to program the entire
array, a hardware programming mode is provided as an alternative to the software-intensive method
previously described.
SyncFlash programming mode implements two command sequence triplets: a program sequence (write)
and a status check sequence (read). The state diagram for these two sequences is illustrated in
Figure 24-24.
Figure 24-24. SyncFlash Program Mode State Diagram
MOTOROLA
COMMAND
LCR
IDLE
Write
NOP
LCR
Addr = 0x40 Addr = 0x70
Bank = A
ACT
Addr = Row
A
Bank = A
WRITE
Addr = Col
A
Bank = A
* — Any address within memory region
SDRAM Memory Controller
ROW
x
ACT
Read
LCR
Bank = *
ACT
Addr = *
Bank = *
READ
Addr = *
Bank = *
Operating Modes
Config
x
READ
24-27