Dct/Idct Irq Status Register; Table 17-27 Dct/Idct Irq Status Register Description - Motorola DragonBall MC9328MX1 Reference Manual

17.3.5.4 DCT/iDCT IRQ Status Register

MMA_DCTIRQSTAT
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Table 17-27. DCT/iDCT IRQ Status Register Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–6
FIFO FULL FIFO Full—Indicates whether the FIFO is full or not. Remains high
Bit 5 until all data is read from the FIFO. Write a 1 to clear.
FIFO EMP FIFO Empty—Indicates whether the FIFO is filled with input data
Bit 4 or not.The bit is cleared automatically when the input FIFO
becomes full. Write a 1 to clear.
ERR INTR Error Interrupt—Indicates whether an error has occurred while
Bit 3 accessing memory through the memory controller. Write a 1 to
clear.
DOUTINTR Data Out Interrupt—Determines when the data out interrupt is
Bit 2 asserted. Write a 1 to clear.
DININTR Data In Interrupt—Determines when the data in interrupt is
Bit 1 asserted. Write a 1 to clear.
DCTCOMP Transform Complete—Indicates whether a transform has
Bit 0 completed. Write a 1 to clear.
MOTOROLA
DCT/iDCT IRQ Status Register
28 27 26 25 24
r r r r r
0 0 0 0 0
12 11 10 9 8
r r r r r
0 0 0 0 0
Description
Multimedia Accelerator (MMA)
23 22 21 20
r r r r
0 0 0 0
0x0000
7 6 5 4
FIFO FIFO
FULL EMP
r r rw rw
0 0 0 0
0x0000
Programming Model
Addr
0x0022240C
19 18 17
r r r
0 0 0
3 2 1
ERR DOUT DIN DCT
INTR INTR INTR COMP
rw rw rw
0 0 0
Settings
0 = Output FIFO is not filled
1 = Output FIFO is filled, some
data left unread
0 = Input FIFO is not filled
1 = Input FIFO is full
0 = No error has occurred
1 = An error has occurred
0 = Data out interrupt has
occurred
1 =Data out interrupt has not
occurred
0 = Data In interrupt has
occurred
1 =Data In interrupt has not
occurred
0 = Transform is not complete
1 = Transform is complete
17-27
16
r
0
0
rw
0