Receive Threshold Register - Motorola DragonBall MC9328MX1 Reference Manual

Table 25-10. Control Register Descriptions (Continued)
Name
ONACK Overrun NACK Enable—Enables/Disables
Bit 3 overrun NACK generation.
ANACK Automatic NACK Enable—Enables/Disables
Bit 2 NACK generation for parity errors or invalid initial
characters when ICM is enabled.
ICM Initial Character Mode—Enables/Disables initial
Bit 1 character mode. ICM is automatically cleared by
hardware when a valid initial character is received.
IC Data Format Control—Configures the SIM to use
Bit 0 either inverse convention or direct convention for
its data format. The IC bit can be controlled by
software, however it is normally set by hardware as
a result of the interpretation of the initial character
when ICM is enabled. There is a two reference
clock cycle delay before the software can read that
IC is set after writing it.
Note: Changing CLK_SEL not only affects the transmit baud rate, it also determines the frequency of the
SmartCard clock driven on the SmartCard port clock pins. The CNTL register must not be written while the SIM
transmitter or receiver is enabled.

25.6.3 Receive Threshold Register

The Receive Threshold Register (RCV_THRESHOLD) determines the number of unread bytes that must
exist in the FIFO to trigger the receive data register full (RDRF) interrupt flag. The RDT field description
for the Receive Threshold Register is provided in Table 25-11.
RCV_THRESHOLD
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
MOTOROLA
Description
Receive Threshold Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
r r r r
0 0 0 0
SmartCard Interface Module (SIM)
0 = NACK generation on overrun is
disabled
1 = NACK generation on overrun is
enabled
0 = NACK generation on errors disabled
1 = NACK generation on errors enabled
0 = Initial character mode disabled
1 = Initial character mode enabled
0 = Direction convention transfers enabled
1 = Inverse convention transfers enabled
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
r r r r rw
0 0 0 0 0
0x0001
Programming Model
Settings
Addr
0x00211008
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
RDT
rw rw rw rw
0 0 0 1
25-25