Table 18-9 Spi 1 Sample Period Control Register And Spi 2 Sample Period Control Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Table 18-8. SPI 1 Test Register and SPI 2 Test Register Description (Continued)
Name
TXCNT TXFIFO Counter—Indicates the number of data words in the
Bits 3–0 TXFIFO.
18.3.6 Sample Period Control Registers
The SPI sample period control registers allow the user to select the clock source for the counter and to set
the wait between data transactions. The wait is only applicable when the SPI module is operating in master
mode.
PERIODREG1
PERIODREG2
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
CSRC
TYPE rw rw rw
0 0 0
RESET
Table 18-9. SPI 1 Sample Period Control Register and
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
CSRC Clock Source—Selects the clock source for the counter.
Bit 15
WAIT Wait—Determines the number of clocks inserted between data
Bits 14–0 transactions (when operating in master mode).
MOTOROLA
Description
SPI 1 Sample Period Control Register
SPI 2 Sample Period Control Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
rw rw rw rw
0 0 0 0
SPI 2 Sample Period Control Register Description
Description
Serial Peripheral Interface Modules (SPI 1 and SPI 2)
0000 = TXFIFO is empty
0001 = 1 data word in TXFIFO
0010 = 2 data words in TXFIFO
0011 = 3 data words in TXFIFO
0100 = 4 data words in TXFIFO
0101 = 5 data words in TXFIFO
0110 = 6 data words in TXFIFO
0111 = 7 data words in TXFIFO
1000 = 8 data words in TXFIFO
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
WAIT
rw rw rw rw rw
0 0 0 0 0
0x0000
Programming Model
Settings
Addr
0x00213014
0x00219014
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
rw rw rw rw
0 0 0 0
Settings
0 = Bit clock
1 = 32.768 kHz clock
0x0000 = 0 clock
0x0001 = 1 clock
0x0002 = 2 clocks
...
0x7FFF = 32768 clocks
18-13