Figure 16-11 Spi Clock Dividers Determine Duty Cycle Of Spi Clock; Table 16-70 Spi Control Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Bluetooth Accelerator (BTA)
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
BYTE_ONLY Byte/Word—Specifies whether the current data is a byte or a
Bit 15 word.
SPI_CLKINV Inverted SPI Clock—Specifies whether the SPI clock output
Bit 14 is inverted.
SPI_CLKDIV3 State 3 Delay—Controls the SPI clock space period. See
Bits 13–12 Figure 16-11 on page 16-80 for details.
SPI_CLKDIV2 State 2 Delay—Controls the SPI clock mark period. See
Bits 11–8 Figure 16-11 on page 16-80 for details.
SPI_CLKDIV1 State 1 Delay—Controls the SPI clock space period. See
Bits 7–4 Figure 16-11 on page 16-80 for details.
Reserved Reserved—This bit is reserved and should read 0.
Bit 3
SPI_MODE SPI Mode Selection—Sets SPI mode according to the radio
Bits 2–0 used.
1
SPI State
SPI_EN
SPI_CLK
Figure 16-11. SPI Clock Dividers Determine Duty Cycle of SPI Clock
16-80
Table 16-70. SPI Control Register Description
Description
2 3 1 2
MC9328MX1 Reference Manual
0 = Normal
1 = Single bytes only
0 = Normal
1 = Inverted
These divider settings determine
the duty cycle division ratio for
high and low signal levels, as
well as for the clock. The ratios
are specified as the target ratios
minus one.
011 = MC13180
100 = SiliconWave
All Other Settings Reserved
3 1 2 3
Settings
2 3
1
MOTOROLA