Interrupt Mask Register; Table 25-15 Interrupt Mask Register Description - Motorola DragonBall MC9328MX1 Reference Manual

25.6.7 Interrupt Mask Register

The bit descriptions and settings for the Interrupt Mask Register (INT_MASK) are provided in
Table 25-15.
INT_MASK
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–10
CWTM Character Wait Time Interrupt Mask—Enables/Disables the
Bit 9 ability of the CWT flag in the RCV_STATUS register to generate
SIM interrupts.
GPCNTM General Purpose Counter Interrupt Mask—Enables/Disables
Bit 8 the ability of the GPCNT flag in the XMT_STATUS register to
generate SIM interrupts.
TDTFM Transmit Data Threshold Interrupt Mask—Enables/Disables
Bit 7 the ability of the TDTF in the XMT_STATUS register to generate
SIM interrupts.
TFOM Transmit FIFO Overfill Error Interrupt
Bit 6 Mask—Enables/Disables the ability of the TFO flag in the
XMT_STATUS register to generate SIM interrupts.
XTM Transmit Threshold Interrupt Mask—Enables/Disables the
Bit 5 ability of the XTE flag in the XMT_STATUS register to generate
SIM interrupts.
TFEIM Transmit FIFO Empty Interrupt Mask—Enables/Disables the
Bit 4 ability of the TFE flag in the XMT_STATUS register to generate
SIM interrupts.
ETCIM Early Transmit Complete Interrupt Mask—Enables/Disables
Bit 3 the ability of the ETC flag in the RCV_STATUS register to
generate SIM interrupts.
MOTOROLA
Interrupt Mask Register
28 27 26 25 24
r r r r
0 0 0 0 0
12 11 10 9 8
CWTM GPCNTM
r r r rw rw
0 0 0 1 1
Table 25-15. Interrupt Mask Register Description
Description
SmartCard Interface Module (SIM)
23 22 21
r r r r
0 0 0
0x0000
7 6 5
TDTFM TFOM XTM TFEIM ETCIM OIM TCIM
rw rw rw
1 1 1
0x03FF
Programming Model
Addr
0x00211018
20 19 18 17
r r r r
0 0 0 0
4 3 2 1
rw rw rw rw
1 1 1 1
Settings
0 = CWT interrupt enabled
1 = CWT interrupt masked
0 = GPCNT interrupt enabled
1 = GPCNT interrupt masked
0 = TDTF interrupt enabled
1 = TDTF interrupt masked
0 = TFO interrupt enabled
1 = TFO interrupt masked
0 = XTE interrupt enabled
1 = XTE interrupt masked
0 = TFE interrupt enabled.
1 = TFE interrupt masked
0 = ETC interrupt enabled
1 = ETC interrupt masked
16
r
0
0
RIM
rw
1
25-31