Figure 29-1 I 2 C Module Block Diagram - Motorola DragonBall MC9328MX1 Reference Manual

2
I C Module
Registers and MC9328MX1 Interface
2
I C Frequency
Divider Register
(IFDR)
Clock
Control
Input
Sync
Serial
Clock
Line
(SCL)
2
29.3 I C System Configuration
2
The I C module uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. For I
compliance, all devices connected to these two signals must have open drain or open collector outputs.
(There is no such requirement for inputs.) The logic AND function is exercised on both lines with external
pull-up resistors.
2
The default state of the I
2
transmit address, the I C module always returns to the default state. Exceptions are described in
Section 29.7.1, "Initialization Sequence."
2
C module is designed to be compatible with The I
The I
Specification, Version 2.1 (Philips Semiconductor: 2000). For detailed
information on system configuration, protocol, and restrictions, see the
Philips I
29-2
IRQ
2
I C Control I
Register
(I2CR)
START, STOP,
and
Arbitration
Control
Serial
Data
Line
(SDA)
2
Figure 29-1. I C Module Block Diagram
C is slave receiver. When not programmed to be a master or responding to a slave
2
C standard.
MC9328MX1 Reference Manual
Internal Bus
Address
Address Decode
2 2
C Status I C Data
Register I/O Register
(I2SR) (I2DR)
In/Out
Data
Shift
Register
Address
Compare
NOTE:
Data
Data MUX
2
I C Address
Register
(IADR)
2
C
2
C Bus
MOTOROLA