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Motorola DSP56800 Manual

Motorola DSP56800 Manual (444 pages)

16-Bit Digital Signal Processor  
Brand: Motorola | Category: Processor | Size: 4.26 MB
Table of contents
Table Of Contents3................................................................................................................................................................
About This Book21................................................................................................................................................................
Dsp56800 Family Architecture25................................................................................................................................................................
Core Overview26................................................................................................................................................................
Peripheral Blocks27................................................................................................................................................................
Family Members29................................................................................................................................................................
Introduction To Digital Signal Processing29................................................................................................................................................................
Summary Of Features33................................................................................................................................................................
For The Latest Information34................................................................................................................................................................
Core Block Diagram35................................................................................................................................................................
Data Arithmetic Logic Unit (alu)37................................................................................................................................................................
Address Generation Unit (agu)37................................................................................................................................................................
Program Controller And Hardware Looping Unit38................................................................................................................................................................
Bus And Bit-manipulation Unit39................................................................................................................................................................
On-chip Emulation (once) Unit39................................................................................................................................................................
Address Buses39................................................................................................................................................................
Data Buses39................................................................................................................................................................
Memory Architecture40................................................................................................................................................................
Blocks Outside The Dsp56800 Core41................................................................................................................................................................
External Data Memory41................................................................................................................................................................
Program Memory42................................................................................................................................................................
Bootstrap Memory42................................................................................................................................................................
Ip-bus Bridge42................................................................................................................................................................
Phase Lock Loop (pll)42................................................................................................................................................................
Dsp56800 Core Programming Model42................................................................................................................................................................
Overview And Architecture46................................................................................................................................................................
Data Alu Input Registers (x0, Y1, And Y0)48................................................................................................................................................................
Data Alu Accumulator Registers48................................................................................................................................................................
Multiply-accumulator (mac) And Logic Unit49................................................................................................................................................................
Barrel Shifter49................................................................................................................................................................
Accumulator Shifter50................................................................................................................................................................
Data Limiter And Mac Output Limiter50................................................................................................................................................................
Accessing The Accumulator Registers51................................................................................................................................................................
Table 3-1 Accessing The Accumulator Registers51................................................................................................................................................................
Accessing An Accumulator By Its Individual Portions52................................................................................................................................................................
Accessing An Entire Accumulator54................................................................................................................................................................
Accessing For Data Alu Operations54................................................................................................................................................................
Writing An Accumulator With A Small Operand54................................................................................................................................................................
Extension Registers As Protection Against Overflow54................................................................................................................................................................
Examples Of Writing The Entire Accumulator55................................................................................................................................................................
General Integer Processing55................................................................................................................................................................
Writing Integer Data To An Accumulator55................................................................................................................................................................
Reading Integer Data From An Accumulator56................................................................................................................................................................
Using 16-bit Results Of Dsp Algorithms56................................................................................................................................................................
Saving And Restoring Accumulators56................................................................................................................................................................
Bit-field Operations On Integers In Accumulators57................................................................................................................................................................
Converting From 36-bit Accumulator To 16-bit Portion57................................................................................................................................................................
Fractional And Integer Data Alu Arithmetic58................................................................................................................................................................
Interpreting Data60................................................................................................................................................................
Table 3-2 Interpretation Of 16-bit Data Values60................................................................................................................................................................
Table 3-3 Interpretation Of 36-bit Data Values60................................................................................................................................................................
Data Formats61................................................................................................................................................................
Signed Fractional61................................................................................................................................................................
Unsigned Fractional61................................................................................................................................................................
Signed Integer62................................................................................................................................................................
Unsigned Integer62................................................................................................................................................................
Addition And Subtraction62................................................................................................................................................................
Logical Operations63................................................................................................................................................................
Multiplication63................................................................................................................................................................
Fractional Multiplication63................................................................................................................................................................
Integer Multiplication64................................................................................................................................................................
Division65................................................................................................................................................................
Unsigned Arithmetic66................................................................................................................................................................
Conditional Branch Instructions For Unsigned Operations66................................................................................................................................................................
Unsigned Multiplication66................................................................................................................................................................
Multi-precision Operations67................................................................................................................................................................
Multi-precision Addition And Subtraction67................................................................................................................................................................
Multi-precision Multiplication67................................................................................................................................................................
Saturation And Data Limiting70................................................................................................................................................................
Data Limiter70................................................................................................................................................................
Table 3-4 Saturation By The Limiter Using The Move Instruction71................................................................................................................................................................
Mac Output Limiter72................................................................................................................................................................
Instructions Not Affected By The Mac Output Limiter73................................................................................................................................................................
Table 3-5 Mac Unit Outputs With Saturation Enabled73................................................................................................................................................................
Rounding74................................................................................................................................................................
Convergent Rounding74................................................................................................................................................................
Two's-complement Rounding75................................................................................................................................................................
Condition Code Generation77................................................................................................................................................................
Bit Destinations—cc Bit Cleared77................................................................................................................................................................
Bit Destinations—cc Bit Set78................................................................................................................................................................
Bit Destinations79................................................................................................................................................................
Special Instruction Types79................................................................................................................................................................
Tst And Tstw Instructions80................................................................................................................................................................
Architecture And Programming Model82................................................................................................................................................................
Address Registers (r0-r3)84................................................................................................................................................................
Stack Pointer Register (sp)84................................................................................................................................................................
Offset Register (n)84................................................................................................................................................................
Modifier Register (m01)85................................................................................................................................................................
Modulo Arithmetic Unit85................................................................................................................................................................
Incrementer/decrementer Unit85................................................................................................................................................................
Addressing Modes86................................................................................................................................................................
Table 4-1 Addressing Mode Forcing Operators86................................................................................................................................................................
Table 4-2 Jump And Branch Forcing Operators86................................................................................................................................................................
Register-direct Modes87................................................................................................................................................................
Data Or Control Register Direct87................................................................................................................................................................
Address Register Direct87................................................................................................................................................................
Address-register-indirect Modes87................................................................................................................................................................
Table 4-3 Addressing Mode—register Direct87................................................................................................................................................................
Table 4-4 Addressing Mode—address Register Indirect88................................................................................................................................................................
No Update: (rn), (sp)89................................................................................................................................................................
Table 4-5 Address-register-indirect Addressing Modes Available89................................................................................................................................................................
Post-increment By 1: (rn)+, (sp)+91................................................................................................................................................................
Post-decrement By 1: (rn)-, (sp)-92................................................................................................................................................................
Post-update By Offset N: (rn)+n, (sp)+n93................................................................................................................................................................
Index By Offset N: (rn+n), (sp+n)94................................................................................................................................................................
Index By Short Displacement: (sp-xx), (r2+xx)95................................................................................................................................................................
Index By Long Displacement: (rn+xxxx), (sp+xxxx)96................................................................................................................................................................
Immediate Data Modes97................................................................................................................................................................
Table 4-6 Addressing Mode—immediate97................................................................................................................................................................
Immediate Data: #xxxx98................................................................................................................................................................
Immediate Short Data: #xx100................................................................................................................................................................
Absolute Addressing Modes100................................................................................................................................................................
Table 4-7 Addressing Mode—absolute100................................................................................................................................................................
Absolute Address (extended Addressing): Xxxx101................................................................................................................................................................
Absolute Short Address (direct Addressing): 102................................................................................................................................................................
I/o Short Address (direct Addressing): 103................................................................................................................................................................
Implicit Reference103................................................................................................................................................................
Addressing Modes Summary103................................................................................................................................................................
Table 4-8 Addressing Mode Summary104................................................................................................................................................................
Agu Address Arithmetic105................................................................................................................................................................
Linear Arithmetic105................................................................................................................................................................
Modulo Arithmetic105................................................................................................................................................................
Modulo Arithmetic Overview105................................................................................................................................................................
Configuring Modulo Arithmetic107................................................................................................................................................................
Table 4-9 Programming M01 For Modulo Arithmetic107................................................................................................................................................................
Supported Memory Access Instructions109................................................................................................................................................................
Simple Circular Buffer Example109................................................................................................................................................................
Setting Up A Modulo Buffer110................................................................................................................................................................
Wrapping To A Different Bank111................................................................................................................................................................
Side Effects Of Modulo Arithmetic112................................................................................................................................................................
When A Pointer Lies Outside A Modulo Buffer112................................................................................................................................................................
Restrictions On The Offset Register112................................................................................................................................................................
Memory Locations Not Available For Modulo Buffers113................................................................................................................................................................
Pipeline Dependencies113................................................................................................................................................................
Program Counter119................................................................................................................................................................
Instruction Latch And Instruction Decoder119................................................................................................................................................................
Interrupt Control Unit119................................................................................................................................................................
Looping Control Unit120................................................................................................................................................................
Loop Counter120................................................................................................................................................................
Loop Address121................................................................................................................................................................
Hardware Stack122................................................................................................................................................................
Status Register122................................................................................................................................................................
Carry (c)—bit 0123................................................................................................................................................................
Overflow (v)—bit 1123................................................................................................................................................................
Zero (z)—bit 2123................................................................................................................................................................
Negative (n)—bit 3123................................................................................................................................................................
Unnormalized (u)—bit 4124................................................................................................................................................................
Extension (e)—bit 5124................................................................................................................................................................
Limit (l)—bit 6124................................................................................................................................................................
Size (sz)—bit 7124................................................................................................................................................................
Interrupt Mask (i1 And I0)—bits 8–9124................................................................................................................................................................
Reserved Sr Bits— Bits 10–14125................................................................................................................................................................
Loop Flag (lf)—bit 15125................................................................................................................................................................
Operating Mode Register125................................................................................................................................................................
Table 5-1 Interrupt Mask Bit Definition125................................................................................................................................................................
Operating Mode Bits (mb And Ma)—bits 1–0126................................................................................................................................................................
Table 5-2 Program Rom Operating Modes126................................................................................................................................................................
External X Memory Bit (ex)—bit 3127................................................................................................................................................................
Saturation (sa)—bit 4127................................................................................................................................................................
Table 5-3 Program Ram Operating Modes127................................................................................................................................................................
Table 5-4 Mac Unit Outputs With Saturation Mode Enabled (sa = 1)127................................................................................................................................................................
Rounding Bit (r)—bit 5128................................................................................................................................................................
Stop Delay Bit (sd)—bit 6128................................................................................................................................................................
Condition Code Bit (cc)—bit 8128................................................................................................................................................................
Nested Looping Bit (nl)—bit 15129................................................................................................................................................................
Reserved Omr Bits—bits 2, 7 And 9–14129................................................................................................................................................................
Software Stack Operation129................................................................................................................................................................
Table 5-5 Looping Status129................................................................................................................................................................
Program Looping130................................................................................................................................................................
Repeat (rep) Looping130................................................................................................................................................................
Do Looping131................................................................................................................................................................
Nested Hardware Do And Rep Looping131................................................................................................................................................................
Terminating A Do Loop131................................................................................................................................................................
Introduction To Moves And Parallel Moves133................................................................................................................................................................
Table 6-1 Memory Space Symbols134................................................................................................................................................................
Instruction Formats135................................................................................................................................................................
Table 6-2 Instruction Formats136................................................................................................................................................................
Programming Model137................................................................................................................................................................
Instruction Groups138................................................................................................................................................................
Arithmetic Instructions138................................................................................................................................................................
Table 6-3 Arithmetic Instructions List138................................................................................................................................................................
Logical Instructions139................................................................................................................................................................
Bit-manipulation Instructions140................................................................................................................................................................
Table 6-4 Logical Instructions List140................................................................................................................................................................
Table 6-5 Bit-field Instruction List140................................................................................................................................................................
Looping Instructions141................................................................................................................................................................
Move Instructions141................................................................................................................................................................
Table 6-6 Loop Instruction List141................................................................................................................................................................
Program Control Instructions143................................................................................................................................................................
Table 6-7 Move Instruction List143................................................................................................................................................................
Table 6-8 Program Control Instruction List143................................................................................................................................................................
Instruction Aliases144................................................................................................................................................................
Andc, Eorc, Orc, And Notc Aliases144................................................................................................................................................................
Table 6-9 Aliases For Logical Instructions With Immediate Data144................................................................................................................................................................
Lsll Alias145................................................................................................................................................................
Asl Alias145................................................................................................................................................................
Clr Alias145................................................................................................................................................................
Table 6-10 Lsll Instruction Alias145................................................................................................................................................................
Table 6-11 Asl Instruction Remapping145................................................................................................................................................................
Pop Alias146................................................................................................................................................................
Dsp56800 Instruction Set Summary146................................................................................................................................................................
Register Field Notation146................................................................................................................................................................
Table 6-12 Clear Instruction Alias146................................................................................................................................................................
Table 6-13 Move Word Instruction Alias—data Memory146................................................................................................................................................................
Table 6-14 Register Fields For General-purpose Writes And Reads147................................................................................................................................................................
Table 6-15 Address Generation Unit (agu) Registers147................................................................................................................................................................
Using The Instruction Summary Tables148................................................................................................................................................................
Table 6-16 Data Alu Registers148................................................................................................................................................................
Instruction Summary Tables149................................................................................................................................................................
Table 6-17 Move Word Instructions150................................................................................................................................................................
Table 6-18 Immediate Move Instructions151................................................................................................................................................................
Table 6-19 Register-to-register Move Instructions151................................................................................................................................................................
Table 6-20 Move Word Instructions—program Memory151................................................................................................................................................................
Table 6-21 Conditional Register Transfer Instructions152................................................................................................................................................................
Table 6-22 Data Alu Multiply Instructions152................................................................................................................................................................
Table 6-23 Data Alu Extended Precision Multiplication Instructions153................................................................................................................................................................
Table 6-24 Data Alu Arithmetic Instructions153................................................................................................................................................................
Table 6-25 Data Alu Miscellaneous Instructions155................................................................................................................................................................
Table 6-26 Data Alu Logical Instructions155................................................................................................................................................................
Table 6-27 Data Alu Shifting Instructions156................................................................................................................................................................
Table 6-28 Agu Arithmetic Instructions157................................................................................................................................................................
Table 6-29 Bit-manipulation Instructions157................................................................................................................................................................
Table 6-30 Branch On Bit-manipulation Instructions158................................................................................................................................................................
Table 6-31 Change Of Flow Instructions159................................................................................................................................................................
Table 6-32 Looping Instructions159................................................................................................................................................................
Table 6-33 Control Instructions160................................................................................................................................................................
Table 6-34 Data Alu Instructions—single Parallel Move161................................................................................................................................................................
The Instruction Pipeline162................................................................................................................................................................
Instruction Processing162................................................................................................................................................................
Table 6-35 Data Alu Instructions—dual Parallel Read162................................................................................................................................................................
Memory Access Processing163................................................................................................................................................................
Reset Processing State165................................................................................................................................................................
Table 7-1 Processing States165................................................................................................................................................................
Normal Processing State166................................................................................................................................................................
Instruction Pipeline Description166................................................................................................................................................................
Instruction Pipeline With Off-chip Memory Accesses167................................................................................................................................................................
Table 7-2 Instruction Pipelining167................................................................................................................................................................
Instruction Pipeline Dependencies And Interlocks168................................................................................................................................................................
Table 7-3 Additional Cycles For Off-chip Memory Accesses168................................................................................................................................................................
Exception Processing State169................................................................................................................................................................
Sequence Of Events In The Exception Processing State169................................................................................................................................................................
Reset And Interrupt Vector Table171................................................................................................................................................................
Table 7-4 Dsp56800 Core Reset And Interrupt Vector Table171................................................................................................................................................................
Interrupt Priority Structure172................................................................................................................................................................
Configuring Interrupt Sources172................................................................................................................................................................
Table 7-5 Interrupt Priority Level Summary172................................................................................................................................................................
Table 7-6 Interrupt Mask Bit Definition In The Status Register172................................................................................................................................................................
Interrupt Sources173................................................................................................................................................................
External Hardware Interrupt Sources174................................................................................................................................................................
Dsp Core Hardware Interrupt Sources175................................................................................................................................................................
Dsp Core Software Interrupt Sources175................................................................................................................................................................
Interrupt Arbitration176................................................................................................................................................................
Table 7-7 Fixed Priority Structure Within An Ipl177................................................................................................................................................................
The Interrupt Pipeline178................................................................................................................................................................
Interrupt Latency180................................................................................................................................................................
Wait Processing State181................................................................................................................................................................
Stop Processing State183................................................................................................................................................................
Debug Processing State186................................................................................................................................................................
Useful Instruction Operations187................................................................................................................................................................
Table 8-1 Operations Synthesized Using Dsp56800 Instructions187................................................................................................................................................................
Jumps And Branches188................................................................................................................................................................
Jrset And Jrclr Operations188................................................................................................................................................................
Br1set And Br1clr Operations189................................................................................................................................................................
Jr1set And Jr1clr Operations189................................................................................................................................................................
Jvs, Jvc, Bvs, And Bvc Operations190................................................................................................................................................................
Other Jumps And Branches On Condition Codes190................................................................................................................................................................
Negation Operations190................................................................................................................................................................
Negw Operation190................................................................................................................................................................
Negating The X0, Y0, Or Y1 Data Alu Registers191................................................................................................................................................................
Negating An Agu Register191................................................................................................................................................................
Negating A Memory Location191................................................................................................................................................................
Register Exchanges192................................................................................................................................................................
Minimum And Maximum Values192................................................................................................................................................................
Max Operation192................................................................................................................................................................
Min Operation193................................................................................................................................................................
Accumulator Sign Extend193................................................................................................................................................................
Unsigned Load Of An Accumulator193................................................................................................................................................................
And 32-bit Shift Operations194................................................................................................................................................................
Small Immediate 16- Or 32-bit Shifts194................................................................................................................................................................
General 16-bit Shifts194................................................................................................................................................................
General 32-bit Arithmetic Right Shifts195................................................................................................................................................................
General 32-bit Logical Right Shifts195................................................................................................................................................................
Arithmetic Shifts By A Fixed Amount196................................................................................................................................................................
Right Shifts (asr12–asr20)196................................................................................................................................................................
Left Shifts (asl16–asl19)198................................................................................................................................................................
Incrementing And Decrementing Operations199................................................................................................................................................................
Positive Dividend And Divisor With Remainder200................................................................................................................................................................
Signed Dividend And Divisor With No Remainder201................................................................................................................................................................
Signed Dividend And Divisor With Remainder202................................................................................................................................................................
Algorithm Examples204................................................................................................................................................................
Overflow Cases205................................................................................................................................................................
Multiple Value Pushes205................................................................................................................................................................
Loops206................................................................................................................................................................
Large Loops (count Greater Than 63)206................................................................................................................................................................
Variable Count Loops207................................................................................................................................................................
Software Loops207................................................................................................................................................................
Nested Loops208................................................................................................................................................................
Recommendations208................................................................................................................................................................
Nested Hardware Do And Rep Loops209................................................................................................................................................................
Comparison Of Outer Looping Techniques210................................................................................................................................................................
Hardware Do Looping In Interrupt Service Routines211................................................................................................................................................................
Early Termination Of A Do Loop211................................................................................................................................................................
Array Indexes212................................................................................................................................................................
Global Or Fixed Array With A Constant212................................................................................................................................................................
Global Or Fixed Array With A Variable213................................................................................................................................................................
Local Array With A Constant213................................................................................................................................................................
Local Array With A Variable213................................................................................................................................................................
Array With An Incrementing Pointer213................................................................................................................................................................
Parameters And Local Variables214................................................................................................................................................................
Time-critical Do Loops215................................................................................................................................................................
Interrupts216................................................................................................................................................................
Setting Interrupt Priorities In Software216................................................................................................................................................................
High Priority Or A Small Number Of Instructions217................................................................................................................................................................
Many Instructions Of Equal Priority217................................................................................................................................................................
Many Instructions And Programmable Priorities218................................................................................................................................................................
Hardware Looping In Interrupt Routines218................................................................................................................................................................
Identifying System Calls By A Number218................................................................................................................................................................
Jumps And Jsrs Using A Register Value219................................................................................................................................................................
Freeing One Hardware Stack Location220................................................................................................................................................................
Multitasking And The Hardware Stack220................................................................................................................................................................
Saving The Hardware Stack221................................................................................................................................................................
Restoring The Hardware Stack221................................................................................................................................................................
Combined Jtag And Once Interface223................................................................................................................................................................
Jtag Port224................................................................................................................................................................
Jtag Capabilities225................................................................................................................................................................
Jtag Port Architecture225................................................................................................................................................................
Once Port226................................................................................................................................................................
Once Port Capabilities227................................................................................................................................................................
Once Port Architecture227................................................................................................................................................................
Command, Status, And Control229................................................................................................................................................................
Breakpoint And Trace229................................................................................................................................................................
Pipeline Save And Restore229................................................................................................................................................................
Fifo History Buffer229................................................................................................................................................................
A.1 Notation231................................................................................................................................................................
Table A-1 Register Fields For General-purpose Writes And Reads231................................................................................................................................................................
Table A-2 Address Generation Unit (agu) Registers232................................................................................................................................................................
Table A-3 Data Alu Registers232................................................................................................................................................................
Table A-4 Address Operands233................................................................................................................................................................
Table A-5 Addressing Mode Operators233................................................................................................................................................................
Table A-6 Miscellaneous Operands233................................................................................................................................................................
Table A-7 Other Symbols234................................................................................................................................................................
A.2 Programming Model235................................................................................................................................................................
A.3 Addressing Modes236................................................................................................................................................................
A.4 Condition Code Computation236................................................................................................................................................................
A.4.1 The Condition Code Bits237................................................................................................................................................................
A.4.1.1 Size (sz)—bit 7237................................................................................................................................................................
A.4.1.2 Limit (l)—bit 6238................................................................................................................................................................
A.4.1.3 Extension In Use (e)—bit 5238................................................................................................................................................................
A.4.1.4 Unnormalized (u)—bit 4239................................................................................................................................................................
A.4.1.5 Negative (n)—bit 3239................................................................................................................................................................
A.4.1.6 Zero (z)—bit 2240................................................................................................................................................................
A.4.1.7 Overflow (v)—bit 1240................................................................................................................................................................
A.4.1.8 Carry (c)—bit 0240................................................................................................................................................................
A.4.2 Effects Of The Operating Mode Register's Sa Bit241................................................................................................................................................................
A.4.3 Effects Of The Omr's Cc Bit241................................................................................................................................................................
A.4.4 Condition Code Summary By Instruction242................................................................................................................................................................
Table A-8 Notation Used For The Condition Code Summary Table242................................................................................................................................................................
Table A-9 Condition Code Summary243................................................................................................................................................................
A.5 Instruction Timing246................................................................................................................................................................
Table A-10 Instruction Timing Symbols247................................................................................................................................................................
Table A-11 Instruction Timing Summary248................................................................................................................................................................
Table A-12 Parallel Move Timing249................................................................................................................................................................
Table A-13 Movec Timing Summary250................................................................................................................................................................
Table A-14 Movem Timing Summary250................................................................................................................................................................
Table A-15 Bit-field Manipulation Timing Summary250................................................................................................................................................................
Table A-16 Branch/jump Instruction Timing Summary250................................................................................................................................................................
Table A-17 Rts Timing Summary251................................................................................................................................................................
Table A-18 Tstw Timing Summary251................................................................................................................................................................
Table A-19 Addressing Mode Timing Summary251................................................................................................................................................................
Table A-20 Memory Access Timing Summary252................................................................................................................................................................
A.6 Instruction Set Restrictions256................................................................................................................................................................
A.7 Instruction Descriptions257................................................................................................................................................................
No Operation Nop366................................................................................................................................................................
Table B-1 Benchmark Summary405................................................................................................................................................................
B.1 Benchmark Code406................................................................................................................................................................
B.1.1 Real Correlation Or Convolution (fir Filter)407................................................................................................................................................................
B.1.2 N Complex Multiplies408................................................................................................................................................................
B.1.3 Complex Correlation Or Convolution (complex Fir)408................................................................................................................................................................
B.1.4 Nth Order Power Series (real, Fractional Data)409................................................................................................................................................................
B.1.5 N Cascaded Real Biquad Iir Filters (direct Form Ii)409................................................................................................................................................................
B.1.6 N Radix 2 Fft Butterflies410................................................................................................................................................................
B.1.7 Lms Adaptive Filter411................................................................................................................................................................
B.1.7.1 Single Precision413................................................................................................................................................................
B.1.7.2 Double Precision414................................................................................................................................................................
B.1.7.3 Double Precision Delayed415................................................................................................................................................................
B.1.8 Vector Multiply-accumulate416................................................................................................................................................................
B.1.9 Energy In A Signal417................................................................................................................................................................
B.1.10 [3x3][1x3] Matrix Multiply418................................................................................................................................................................
B.1.11 [nxn][nxn] Matrix Multiply419................................................................................................................................................................
B.1.12 N Point 3x3 2-d Fir Convolution421................................................................................................................................................................
Table B-2 Variable Descriptions421................................................................................................................................................................
B.1.13 Sine-wave Generation424................................................................................................................................................................
B.1.13.1 Double Integration Technique424................................................................................................................................................................
B.1.13.2 Second Order Oscillator425................................................................................................................................................................
B.1.14 Array Search426................................................................................................................................................................
B.1.14.1 Index Of The Highest Signed Value426................................................................................................................................................................
B.1.14.2 Index Of The Highest Positive Value426................................................................................................................................................................
B.1.15 Proportional Integrator Differentiator (pid) Algorithm427................................................................................................................................................................
B.1.16 Autocorrelation Algorithm428................................................................................................................................................................

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