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Motorola DSP56800 manual available for free PDF download: Manual
Motorola DSP56800 Manual (444 pages)
16-Bit Digital Signal Processor
Brand:
Motorola
| Category:
Computer Hardware
| Size: 4.26 MB
Table of Contents
Table of Contents
3
About this Book
21
Chapter 1 Introduction
25
DSP56800 Family Architecture
25
Figure 1-1 DSP56800-Based DSP Microcontroller Chip
25
Core Overview
26
Peripheral Blocks
27
Figure 1-2 DSP56800 Core Block Diagram
27
Family Members
29
Introduction to Digital Signal Processing
29
Figure 1-3 Example of Chip Built Around the DSP56800 Core
29
Figure 1-4 Analog Signal Processing
30
Figure 1-5 Digital Signal Processing
31
Figure 1-6 Mapping DSP Algorithms into Hardware
32
Summary of Features
33
For the Latest Information
34
Chapter 2 Core Architecture Overview
35
Core Block Diagram
35
Figure 2-1 DSP56800 Core Block Diagram
36
Address Generation Unit (AGU)
37
Data Arithmetic Logic Unit (ALU)
37
Program Controller and Hardware Looping Unit
38
Address Buses
39
Bus and Bit-Manipulation Unit
39
Data Buses
39
On-Chip Emulation (Once) Unit
39
Figure 2-2 DSP56800 Memory Spaces
40
Memory Architecture
40
Blocks Outside the DSP56800 Core
41
External Data Memory
41
Figure 2-3 Sample DSP56800-Family Chip Block Diagram
41
Bootstrap Memory
42
DSP56800 Core Programming Model
42
IP-BUS Bridge
42
Phase Lock Loop (PLL)
42
Program Memory
42
Figure 2-4 DSP56800 Core Programming Model
43
Chapter 3 Data Arithmetic Logic Unit
45
Overview and Architecture
46
Figure 3-1 Data ALU Block Diagram
47
Data ALU Accumulator Registers
48
Data ALU Input Registers (X0, Y1, and Y0)
48
Figure 3-2 Data ALU Programming Model
48
Barrel Shifter
49
Multiply-Accumulator (MAC) and Logic Unit
49
Accumulator Shifter
50
Data Limiter and MAC Output Limiter
50
Figure 3-3 Right and Left Shifts through the Multi-Bit Shifting Unit
50
Accessing the Accumulator Registers
51
Table 3-1 Accessing the Accumulator Registers
51
Accessing an Accumulator by Its Individual Portions
52
Figure 3-4 Writing the Accumulator Extension Registers (F2)
52
Figure 3-5 Reading the Accumulator Extension Registers (F2)
53
Figure 3-6 Writing the Accumulator by Portions
53
Accessing an Entire Accumulator
54
Accessing for Data ALU Operations
54
Extension Registers as Protection against Overflow
54
Writing an Accumulator with a Small Operand
54
Examples of Writing the Entire Accumulator
55
General Integer Processing
55
Figure 3-7 Writing the Accumulator as a Whole
55
Writing Integer Data to an Accumulator
55
Reading Integer Data from an Accumulator
56
Saving and Restoring Accumulators
56
Using 16-Bit Results of DSP Algorithms
56
Bit-Field Operations on Integers in Accumulators
57
Converting from 36-Bit Accumulator to 16-Bit Portion
57
Fractional and Integer Data ALU Arithmetic
58
Figure 3-8 Bit Weightings and Operand Alignments
59
Interpreting Data
60
Table 3-2 Interpretation of 16-Bit Data Values
60
Table 3-3 Interpretation of 36-Bit Data Values
60
Data Formats
61
Signed Fractional
61
Unsigned Fractional
61
Signed Integer
62
Unsigned Integer
62
Addition and Subtraction
62
Figure 3-9 Word-Sized Integer Addition Example
62
Logical Operations
63
Multiplication
63
Figure 3-10 Comparison of Integer and Fractional Multiplication
63
Fractional Multiplication
63
Figure 3-11 MPY Operation-Fractional Arithmetic
64
Integer Multiplication
64
Division
65
Figure 3-12 Integer Multiplication (IMPY)
65
Unsigned Arithmetic
66
Conditional Branch Instructions for Unsigned Operations
66
Unsigned Multiplication
66
Multi-Precision Operations
67
Multi-Precision Addition and Subtraction
67
Multi-Precision Multiplication
67
Figure 3-13 Single-Precision Times Double-Precision Signed Multiplication
68
Data Limiter
70
Saturation and Data Limiting
70
Table 3-4 Saturation by the Limiter Using the MOVE Instruction
71
Figure 3-14 Example of Saturation Arithmetic
72
MAC Output Limiter
72
Instructions Not Affected by the MAC Output Limiter
73
Table 3-5 MAC Unit Outputs with Saturation Enabled
73
Convergent Rounding
74
Rounding
74
Figure 3-15 Convergent Rounding
75
Two's-Complement Rounding
75
Figure 3-16 Two's-Complement Rounding
76
36-Bit Destinations-CC Bit Cleared
77
Condition Code Generation
77
20-Bit Destinations-CC Bit Cleared
78
36-Bit Destinations-CC Bit Set
78
16-Bit Destinations
79
Special Instruction Types
79
TST and TSTW Instructions
80
Unsigned Arithmetic
80
Chapter 4 Address Generation Unit
81
Architecture and Programming Model
82
Figure 4-1 Address Generation Unit Block Diagram
83
Figure 4-2 Address Generation Unit Programming Model
83
Address Registers (R0-R3)
84
Offset Register (N)
84
Stack Pointer Register (SP)
84
Incrementer/Decrementer Unit
85
Modifier Register (M01)
85
Modulo Arithmetic Unit
85
Addressing Modes
86
Table 4-1 Addressing Mode Forcing Operators
86
Table 4-2 Jump and Branch Forcing Operators
86
Address-Register-Indirect Modes
87
Register-Direct Modes
87
Address Register Direct
87
Data or Control Register Direct
87
Table 4-3 Addressing Mode-Register Direct
87
Table 4-4 Addressing Mode-Address Register Indirect
88
No Update: (Rn), (SP)
89
Table 4-5 Address-Register-Indirect Addressing Modes Available
89
Figure 4-3 Address Register Indirect: no Update
90
Figure 4-4 Address Register Indirect: Post-Increment
91
Post-Increment by 1: (Rn)+, (SP)
91
Figure 4-5 Address Register Indirect: Post-Decrement
92
Post-Decrement by 1: (Rn)-, (SP)
92
Figure 4-6 Address Register Indirect: Post-Update by Offset N
93
Post-Update by Offset N: (Rn)+N, (SP)+N
93
Figure 4-7 Address Register Indirect: Indexed by Offset N
94
Index by Offset N: (Rn+N), (SP+N)
94
Figure 4-8 Address Register Indirect: Indexed by Short Displacement
95
Index by Short Displacement: (SP-XX), (R2+XX)
95
Figure 4-9 Address Register Indirect: Indexed by Long Displacement
96
Index by Long Displacement: (Rn+XXXX), (Sp+XXXX)
96
Immediate Data Modes
97
Table 4-6 Addressing Mode-Immediate
97
Figure 4-10 Special Addressing: Immediate Data
98
Immediate Data: #XXXX
98
Figure 4-11 Special Addressing: Immediate Short Data
99
Immediate Short Data: #XX
100
Absolute Addressing Modes
100
Table 4-7 Addressing Mode-Absolute
100
Absolute Address (Extended Addressing): XXXX
101
Figure 4-12 Special Addressing: Absolute Address
101
Absolute Short Address (Direct Addressing): <Aa
102
Figure 4-13 Special Addressing: Absolute Short Address
102
I/O Short Address (Direct Addressing): <Pp
103
Addressing Modes Summary
103
Figure 4-14 Special Addressing: I/O Short Address
103
Implicit Reference
103
Table 4-8 Addressing Mode Summary
104
AGU Address Arithmetic
105
Linear Arithmetic
105
Modulo Arithmetic
105
Modulo Arithmetic Overview
105
Figure 4-15 Circular Buffer
106
Configuring Modulo Arithmetic
107
Table 4-9 Programming M01 for Modulo Arithmetic
107
Figure 4-17 Simple Five-Location Circular Buffer
109
Simple Circular Buffer Example
109
Supported Memory Access Instructions
109
Setting up a Modulo Buffer
110
Wrapping to a Different Bank
111
Figure 4-18 Linear Addressing with a Modulo Modifier
112
Restrictions on the Offset Register
112
Side Effects of Modulo Arithmetic
112
When a Pointer Lies Outside a Modulo Buffer
112
Memory Locations Not Available for Modulo Buffers
113
Pipeline Dependencies
113
Chapter 5
117
Program Controller
117
Architecture and Programming Model
117
Figure 5-1 Program Controller Block Diagram
118
Figure 5-2 Program Controller Programming Model
119
Instruction Latch and Instruction Decoder
119
Interrupt Control Unit
119
Program Counter
119
Loop Counter
120
Looping Control Unit
120
Figure 5-3 Accessing the Loop Count Register (LC)
121
Loop Address
121
Hardware Stack
122
Status Register
122
Figure 5-4 Status Register Format
123
Carry (C)—Bit 0
123
Negative (N)—Bit 3
123
Overflow (V)—Bit 1
123
Zero (Z)—Bit 2
123
Extension (E)—Bit 5
124
Interrupt Mask (I1 and I0)—Bits 8–9
124
Limit (L)—Bit 6
124
Size (Sz)—Bit 7
124
Unnormalized (U)—Bit 4
124
Loop Flag (Lf)—Bit 15
125
Reserved SR Bits— Bits 10–14
125
Operating Mode Register
125
Table 5-1 Interrupt Mask Bit Definition
125
Operating Mode Bits (MB and Ma)—Bits 1–0
126
Figure 5-5 Operating Mode Register (OMR) Format
126
External X Memory Bit (Ex)—Bit 3
127
Saturation (Sa)—Bit 4
127
Table 5-2 Program ROM Operating Modes
126
Table 5-3 Program RAM Operating Modes
127
Table 5-4 MAC Unit Outputs with Saturation Mode Enabled (SA = 1)
127
Condition Code Bit (CC)—Bit 8
128
Rounding Bit (R)—Bit 5
128
Stop Delay Bit (Sd)—Bit 6
128
Nested Looping Bit (Nl)—Bit 15
129
Reserved OMR Bits—Bits 2, 7 and 9–14
129
Software Stack Operation
129
Table 5-5 Looping Status
129
Program Looping
130
DO Looping
131
Nested Hardware DO and REP Looping
131
Terminating a DO Loop
131
Chapter 6 Instruction Set Introduction
133
Introduction to Moves and Parallel Moves
133
Figure 6-1 Single Parallel Move
134
Table 6-1 Memory Space Symbols
134
Figure 6-2 Dual Parallel Move
135
Instruction Formats
135
Table 6-2 Instruction Formats
136
Figure 6-3 DSP56800 Core Programming Model
137
Instruction Groups
138
Arithmetic Instructions
138
Table 6-3 Arithmetic Instructions List
138
Logical Instructions
139
Bit-Manipulation Instructions
140
Table 6-4 Logical Instructions List
140
Table 6-5 Bit-Field Instruction List
140
Looping Instructions
141
Move Instructions
141
Table 6-6 Loop Instruction List
141
Program Control Instructions
143
Table 6-7 Move Instruction List
143
Table 6-8 Program Control Instruction List
143
ANDC, EORC, ORC, and NOTC Aliases
144
Instruction Aliases
144
Table 6-9 Aliases for Logical Instructions with Immediate Data
144
LSLL Alias
145
ASL Alias
145
CLR Alias
145
Table 6-10 LSLL Instruction Alias
145
Table 6-11 ASL Instruction Remapping
145
DSP56800 Instruction Set Summary
146
POP Alias
146
Register Field Notation
146
Table 6-12 Clear Instruction Alias
146
Table 6-13 Move Word Instruction Alias-Data Memory
146
Table 6-14 Register Fields for General-Purpose Writes and Reads
147
Table 6-15 Address Generation Unit (AGU) Registers
147
Table 6-16 Data ALU Registers
148
Using the Instruction Summary Tables
148
Instruction Summary Tables
149
Table 6-17 Move Word Instructions
150
Table 6-18 Immediate Move Instructions
151
Table 6-19 Register-To-Register Move Instructions
151
Table 6-20 Move Word Instructions-Program Memory
151
Table 6-21 Conditional Register Transfer Instructions
152
Table 6-22 Data ALU Multiply Instructions
152
Table 6-23 Data ALU Extended Precision Multiplication Instructions
153
Table 6-24 Data ALU Arithmetic Instructions
153
Table 6-25 Data ALU Miscellaneous Instructions
155
Table 6-26 Data ALU Logical Instructions
155
Table 6-27 Data ALU Shifting Instructions
156
Table 6-28 AGU Arithmetic Instructions
157
Table 6-29 Bit-Manipulation Instructions
157
Table 6-30 Branch on Bit-Manipulation Instructions
158
Table 6-31 Change of Flow Instructions
159
Table 6-32 Looping Instructions
159
Table 6-33 Control Instructions
160
Table 6-34 Data ALU Instructions-Single Parallel Move
161
Instruction Processing
162
Table 6-35 Data ALU Instructions-Dual Parallel Read
162
The Instruction Pipeline
162
Figure 6-4 Pipelining
163
Memory Access Processing
163
Chapter 7 Interrupts and the Processing States
165
Reset Processing State
165
Table 7-1 Processing States
165
Instruction Pipeline Description
166
Normal Processing State
166
Instruction Pipeline with Off-Chip Memory Accesses
167
Table 7-2 Instruction Pipelining
167
Instruction Pipeline Dependencies and Interlocks
168
Table 7-3 Additional Cycles for Off-Chip Memory Accesses
168
Exception Processing State
169
Sequence of Events in the Exception Processing State
169
Figure 7-1 Interrupt Processing
170
Table 7-4 DSP56800 Core Reset and Interrupt Vector Table
171
Configuring Interrupt Sources
172
Interrupt Priority Structure
172
Table 7-5 Interrupt Priority Level Summary
172
Table 7-6 Interrupt Mask Bit Definition in the Status Register
172
Figure 7-2 Example Interrupt Priority Register
173
Figure 7-3 Example On-Chip Peripheral and IRQ Interrupt Programming
173
Interrupt Sources
173
External Hardware Interrupt Sources
174
DSP Core Hardware Interrupt Sources
175
DSP Core Software Interrupt Sources
175
Figure 7-4 Illegal Instruction Interrupt Servicing
176
Interrupt Arbitration
176
Table 7-7 Fixed Priority Structure Within an IPL
177
The Interrupt Pipeline
178
Figure 7-5 Interrupt Service Routine
179
Figure 7-6 Repeated Illegal Instruction
180
Interrupt Latency
180
Figure 7-7 Interrupting a REP Instruction
181
Wait Processing State
181
Figure 7-8 Wait Instruction Timing
182
Figure 7-9 Simultaneous Wait Instruction and Interrupt
182
Figure 7-10 STOP Instruction Sequence
183
Stop Processing State
183
Figure 7-11 STOP Instruction Sequence
184
Figure 7-12 STOP Instruction Sequence Recovering with RESET
185
Debug Processing State
186
Chapter 8 Software Techniques
187
Table 8-1 Operations Synthesized Using DSP56800 Instructions
187
Useful Instruction Operations
187
Jumps and Branches
188
JRSET and JRCLR Operations
188
BR1SET and BR1CLR Operations
189
JR1SET and JR1CLR Operations
189
JVS, JVC, BVS, and BVC Operations
190
Other Jumps and Branches on Condition Codes
190
Negation Operations
190
NEGW Operation
190
Negating a Memory Location
191
Negating an AGU Register
191
Negating the X0, Y0, or Y1 Data ALU Registers
191
Minimum and Maximum Values
192
MAX Operation
192
MIN Operation
193
Register Exchanges
192
Accumulator Sign Extend
193
Unsigned Load of an Accumulator
193
And 32-Bit Shift Operations
194
General 16-Bit Shifts
194
Small Immediate 16- or 32-Bit Shifts
194
General 32-Bit Arithmetic Right Shifts
195
General 32-Bit Logical Right Shifts
195
Arithmetic Shifts by a Fixed Amount
196
Right Shifts (ASR12–ASR20)
196
Left Shifts (ASL16–ASL19)
198
Division
199
Incrementing and Decrementing Operations
199
Positive Dividend and Divisor with Remainder
200
Signed Dividend and Divisor with no Remainder
201
Signed Dividend and Divisor with Remainder
202
Algorithm Examples
204
Multiple Value Pushes
205
Overflow Cases
205
Large Loops (Count Greater than 63)
206
Loops
206
Software Loops
207
Variable Count Loops
207
Nested Loops
208
Recommendations
208
Nested Hardware DO and REP Loops
209
Comparison of Outer Looping Techniques
210
Early Termination of a DO Loop
211
Hardware DO Looping in Interrupt Service Routines
211
Array Indexes
212
Global or Fixed Array with a Constant
212
Array with an Incrementing Pointer
213
Global or Fixed Array with a Variable
213
Local Array with a Constant
213
Local Array with a Variable
213
Parameters and Local Variables
214
Figure 8-1 Example of a DSP56800 Stack Frame
215
Time-Critical DO Loops
215
Interrupts
216
Setting Interrupt Priorities in Software
216
High Priority or a Small Number of Instructions
217
Many Instructions of Equal Priority
217
Hardware Looping in Interrupt Routines
218
Identifying System Calls by a Number
218
Many Instructions and Programmable Priorities
218
Jumps and Jsrs Using a Register Value
219
Freeing One Hardware Stack Location
220
Multitasking and the Hardware Stack
220
Restoring the Hardware Stack
221
Chapter 9 JTAG and On-Chip Emulation (Once™)
223
Saving the Hardware Stack
221
Combined JTAG and Once Interface
223
Figure 9-1 Jtag/Once Interface Block Diagram
224
JTAG Port
224
JTAG Capabilities
225
JTAG Port Architecture
225
Figure 9-2 JTAG Block Diagram
226
Once Port
226
Once Port Architecture
227
Once Port Capabilities
227
Figure 9-3 Once Block Diagram
228
Breakpoint and Trace
229
Command, Status, and Control
229
FIFO History Buffer
229
Pipeline Save and Restore
229
A.1 Notation
231
Table A-1 Register Fields for General-Purpose Writes and Reads
231
Table A-2 Address Generation Unit (AGU) Registers
232
Table A-3 Data ALU Registers
232
Table A-4 Address Operands
233
Table A-5 Addressing Mode Operators
233
Table A-6 Miscellaneous Operands
233
Table A-7 Other Symbols
234
A.2 Programming Model
235
Figure A-1 DSP56800 Core Programming Model
235
A.3 Addressing Modes
236
A.4 Condition Code Computation
236
A.4.1 the Condition Code Bits
237
A.4.1.1 Size (Sz)—Bit 7
237
Figure A-2 Status Register (SR
237
A.4.1.2 Limit (L)—Bit 6
238
A.4.1.3 Extension in Use (E)—Bit 5
238
A.4.1.4 Unnormalized (U)—Bit 4
239
A.4.1.5 Negative (N)—Bit 3
239
A.4.1.6 Zero (Z)—Bit 2
240
A.4.1.7 Overflow (V)—Bit 1
240
A.4.1.8 Carry (C)—Bit 0
240
A.4.2 Effects of the Operating Mode Register's SA Bit
241
A.4.3 Effects of the Omr's CC Bit
241
A.4.4 Condition Code Summary by Instruction
242
Table A-8 Notation Used for the Condition Code Summary Table
242
Table A-9 Condition Code Summary
243
A.5 Instruction Timing
246
Table A-10 Instruction Timing Symbols
247
Table A-11 Instruction Timing Summary
248
Table A-12 Parallel Move Timing
249
Table A-13 MOVEC Timing Summary
250
Table A-14 MOVEM Timing Summary
250
Table A-15 Bit-Field Manipulation Timing Summary
250
Table A-16 Branch/Jump Instruction Timing Summary
250
Table A-17 RTS Timing Summary
251
Table A-18 TSTW Timing Summary
251
Table A-19 Addressing Mode Timing Summary
251
Table A-20 Memory Access Timing Summary
252
A.6 Instruction Set Restrictions
256
A.7 Instruction Descriptions
257
And
265
Asll
270
Asr
272
Asrac
274
Asrr
276
Bcc
278
Bfchg - T
280
Bfclr - T
282
Bfset - T
284
Bftsth - T
286
Bftstl - T
288
Bra
289
Brclr - T
290
Brset - T
292
Clr
294
Enddo
307
Eor
309
Illegal
313
Impy
314
Jcc
318
Jmp
320
Jsr
321
Lea
322
Lsl
323
Lsll
325
Lsr
327
Lsrac
329
Lsrr
331
No Operation Nop
366
Table B-1 Benchmark Summary
405
B.1 Benchmark Code
406
B.1.1 Real Correlation or Convolution (FIR Filter)
407
B.1.2 N Complex Multiplies
408
B.1.3 Complex Correlation or Convolution (Complex FIR)
408
B.1.4 Nth Order Power Series (Real, Fractional Data)
409
B.1.5 N Cascaded Real Biquad IIR Filters (Direct Form II)
409
Figure B-1 N Radix 2 FFT Butterflies Memory Map
410
Figure B-2 LMS Adaptive Filter Graphic Representation
411
Figure B-3 LMS Adaptive Filter-Single Precision Memory Map
413
B.1.7.1 Single Precision
413
Figure B-4 LMS Adaptive Filter-Double Precision Memory Map
414
B.1.7.2 Double Precision
414
Figure B-5 LMS Adaptive Filter-Double Precision Delayed Memory Map
415
Figure B-6 Vector Multiply-Accumulate
416
B.1.9 Energy in a Signal
417
Figure B-7 [3X3][1X3] Matrix Multiply
418
Figure B-8 [Nxn][Nxn] Matrix Multiply
419
B.1.12 N Point 3X3 2-D FIR Convolution
421
Table B-2 Variable Descriptions
421
Figure B-9 3X3 Coefficient Mask
421
Figure B-10 Image Stored as 514X514 Array
421
B.1.13 Sine-Wave Generation
424
Figure B-11 Sine Wave Generator-Double Integration Technique
424
Figure B-12 Sine Wave Generator-Second Order Oscillator
425
B.1.14 Array Search
426
B.1.14.1 Index of the Highest Signed Value
426
B.1.14.2 Index of the Highest Positive Value
426
Figure B-13 Proportional Integrator Differentiator Algorithm
427
B.1.16 Autocorrelation Algorithm
428
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