Uart Test Register 1; Table 27-29 Uart1 Test Register 1 And Uart2 Test Register 1 Description - Motorola DragonBall MC9328MX1 Reference Manual

Universal Asynchronous Receiver/Transmitters (UART) Modules

27.7.17 UART Test Register 1

The UART Test Register 1 controls the various test features of the UART module.
UTS_1
UTS_2
BIT 31 30
TYPE r r
0 0
RESET
BIT 15 14
FRCP
TYPE r r
0 0
RESET
Table 27-29. UART1 Test Register 1 and UART2 Test Register 1 Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–14
FRCPERR Force Parity Error—Forces the transmitter to generate a parity
Bit 13 error if parity is enabled. FRCPERR is provided for system
debugging.
LOOP Loop TX and RX for Test—Controls loopback for test purposes.
Bit 12 When LOOP is high, the receiver input is internally connected to the
transmitter and ignores the RXD pin. The transmitter is unaffected
by LOOP.
Reserved Reserved—These bits are reserved and should read 0.
Bits 11–7
TXEMPTY TxFIFO Empty—Indicates that the TxFIFO is empty.
Bit 6
RXEMPTY RxFIFO Empty—Indicates the RxFIFO is empty.
Bit 5
TXFULL TxFIFO FULL—Indicates the TxFIFO is full.
Bit 4
RXFULL RxFIFO FULL—Indicates the RxFIFO is full.
Bit 3
Reserved Reserved—These bits are reserved and should read 0.
Bits 2–1
27-50
UART1 Test Register 1
UART2 Test Register 1
29 28 27 26 25
r r r r r
0 0 0 0 0
13 12 11 10 9
LOOP
ERR
rw rw r rw r
0 0 0 0 0
Description
MC9328MX1 Reference Manual
24 23 22 21
r r r r
0 0 0 0
0x0000
8 7 6 5
TX RX
EMPTY EMPTY
r r r r
0 0 1 1
0x0060
Addr
0x002060D0
0x002070D0
20 19 18 17 16
r r r r
0 0 0 0
4 3 2 1
TX RX SOFT
FULL FULL RST
r r r r
0 0 0 0
Settings
0 = Generate normal parity
1 = Generate inverted parity
(error)
0 = Normal receiver operation
1 = Internally connect the
transmitter output to the
receiver inpu t
0 = The TxFIFO is not empty
1 = The TxFIFO is empty
0 = The RxFIFO is not empty
1 = The RxFIFO is empty
0 = The TxFIFO is not full
1 = The TxFIFO is full
0 = The RxFIFO is not full
1 = The RxFIFO is full
MOTOROLA
r
0
0
r
0