Peripheral Control Register; Table 7-10 Peripheral Access Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Name
Reserved Reserved—These bits are reserved and should read 1.
Bits 31–16
ACCESS Access Control—Each bit controls the access mode of the
Bits 15–1 corresponding peripheral.
Reserved Reserved—This bit is reserved and should read 1.
Bit 0

7.2.3 Peripheral Control Register

These registers are to tell the AIPI whether or not the IP bus peripheral corresponding to the bit location in
the register can be accessed in their natural size only. When set to 1, only byte access is allowed on an 8-bit
peripheral, only halfword access is allowed on a 16-bit peripheral, and only word access is allowed on a
32-bit peripheral. When set to 1, any access other than natural size that is attempted on the peripheral
results in an error response and no IP bus activity occurs.
The least significant bit in the PCR is a read-only bit and the AIPI registers are not governed by this bit.
Bits 31 through 16 in both registers are preset to 0 and the fields are reserved and can only be read.
PCR_1
PCR_2
BIT 31 30 29
TYPE
0 0 0
PCR_1
RESET
0 0 0
PCR_2
RESET
BIT 15 14 13
TYPE rw rw rw
0 0 0
PCR_1
RESET
0 0 0
PCR_2
RESET
MOTOROLA
Table 7-10. Peripheral Access Register Description
Description
AIPI1 Peripheral Control Register
AIPI2 Peripheral Control Register
28 27 26 25
0 0 0 0
0 0 0 0
12 11 10 9
ACCESS_MODE
rw rw rw rw
0 0 0 0
0 0 0 0
AHB to IP Bus Interface (AIPI)
24 23 22 21 20
0 0 0 0 0
0x0000
0 0 0 0 0
0x0000
8 7 6 5 4
rw rw rw rw rw
0 0 0 0 0
0x0000
0 0 0 0 0
0x0000
Programming Model
Settings
0 = Assigned peripheral
determines access
mode.
1 = the corresponding
peripheral is a
supervisor access
only peripheral.
Addr
0x0020000C
0x0021000C
19 18 17 16
0 0 0 0
0 0 0 0
3 2 1 0
rw rw rw r
0 0 0 0
0 0 0 0
7-15