Motorola DragonBall MC9328MX1 Reference Manual page 560

Memory Stick Host Controller (MSHC) Module
Table 21-11. Memory Stick Interrupt Control/Status Register Description (Continued)
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 12–8
RDY Ready—Indicates whether communications with the memory stick are in
Bit 7 progress or have ended. Clear by writing to the Memory Stick Command
Register. MSIRQ asserts when RDY transitions from 0 to 1 to signal that
the protocol has ended. An internal interrupt request (MSIRQ) for this bit
is negated by reading the MSICS register (when INTEN = 1).
Note: Data cannot be written to the Memory Stick Command Register
while the protocol is executing.
SIF Serial I/F Interrupt—Indicates that a Serial I/F Interrupt has been
Bit 6 generated. For SIF, an interrupt signal is output separately from RDY.
(See Figure 21-3, "Memory Stick Interrupt Transfer State (BS0)
Operation," on page 21-6).
Cleared by writing to the Memory Stick Command Register.
An internal interrupt request (MSIRQ) for this bit is negated by reading
the MSICS register (when INTEN = 1).
DRQ Data Transfer Request—Indicates that a data transfer request condition
Bit 5 occurred. The DRQ bit can be changed only when the MSICS bit DRQSL
is 1. Cleared by writing to the FIFO (when PID is a write command) or
reading the FIFO (when PID is a read command), and then an internal
interrupt request (MSIRQ) is negated (when DRQSL = 1). Also the
interrupt request (MSIRQ) for this bit is negated by reading the MSICS
register.
When the DRQEN bit of the MSDRQC register is set to 0, the internal
DMA request signal is not generated even when this DRQ bit is 1.
PIN Parallel Input—Indicates whether the parallel input level has changed
Bit 4 on pins MS_PI [1:0]. This bit is cleared by reading the MSPPCD. An
internal interrupt request (MSIRQ) for this bit is negated by reading the
MSICS register (when INTEN = 1).
Reserved Reserved—This bit is reserved and should read 0.
Bit 3
FAE FIFO Access Error—Indicates that a FIFO access error occurred.
Bit 2 Cleared when the MSFAECS register is read. This status bit is
enabled/disabled with the FAEEN bit of the MSFAECS register. An
internal interrupt request (MSIRQ) for this bit is negated by reading the
MSICS register (when INTEN = 1).
CRC CRC Error—Indicates that a CRC error occurred. Cleared when data is
Bit 1 written to the Memory Stick Command Register.
BS output is set to Low level when a CRC error occurs. Also, RDY
becomes 1 and an interrupt signal is output. An internal interrupt request
(MSIRQ) for this bit is negated by reading the MSICS register (when
INTEN = 1).
21-18
Description
NOTE:
MC9328MX1 Reference Manual
Setting
0 = Protocol in progress
1 = Protocol ended
0 = No serial I/F Interrupt
1 = Serial I/F Interrupt
generated
0 = No data transfer
request condition
occurs
1 = Data transfer request
condition occurs
0 = Parallel Input level
unchanged
1 = Parallel Input level
change
0 = No FIFO access error
1 = FIFO access error
occurred
0 = No CRC error
1 = CRC error occurred
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