Normal Operating Mode; Master / Synchronous Mode; Ssi Clock And Frame Sync Generation; Figure 30-3 Ssi Clocking - Motorola DragonBall MC9328MX1 Reference Manual

Synchronous Serial Interface (SSI)
30.2.1 SSI Clocking
The SSI uses the following clocks:
• Serial bit clock—Serially clocks the data bits in and out of the SSI port
• Word clock—Counts the number of data bits per word (8, 10, 12, or 16 bits)
• Frame clock—Counts the number of words in a frame
• SYS_CLK—Input Clock from the PLL Clock Controller Module (PerCLK3). Made available on
an output pin in synchronous master mode.

30.2.1.1 Normal Operating Mode

In normal operating mode, when the I
Control/Status Register (SCSR) are both clear, the serial bit clock is available on the serial transmit
clock (SSI_TXCLK) and serial receive clock (SSI_RXCLK) pins. The word clock is an internal clock that
determines when transmission of an 8-, 10-, 12-, or 16-bit word is complete. The word clock also clocks
the frame clock, which counts the number of words in the frame. The frame sync clock is available on the
SSI_TXFS and SSI_RXFS frame sync pins because a frame sync is generated after the correct number of
words in the frame are transmitted/received. See Section 30.5, "SSI Operating Modes," on page 30-38 for
a detail description about the SSI operating modes.

30.2.1.2 Master / Synchronous Mode

In master mode and synchronous mode, the unused SSI_RXCLK pin outputs the serial system
clock (SYS_CLK) enabled by the SYS_CLK_EN bit in the SSI Control/Status Register (SCSR). The
SYS_CLK (PerCLK3) is the input clock into the SSI module. The SSI Clock Generator uses the word
length (WL), prescaler range (PSR), prescaler modulus select (PM), and frame rate divider control (DC) to
generate the other clocks from SYS_CLK (PerCLK3). The relationship between the clocks and the
dividers is shown in Figure 30-3. A serial bit clock may be received from a SSI clock pin or can be
generated internally from the PerCLK3 clock by a series of dividers, as shown in Figure 30-4.
Serial Bit Clock

30.2.2 SSI Clock and Frame Sync Generation

Data clock and frame sync signals are generated internally by the MC9328MX1 or can be obtained from
external sources. When generated internally, the SSI clock generator derives bit clock and frame sync
signals from an input clock signal. The SSI clock generator consists of a selectable, fixed prescaler and a
programmable prescaler for bit rate clock generation. In gated clock mode, the data clock is valid only
when data is being transmitted. If the pull-up is disabled for this pin in the GPIO Module's Pull-Up Enable
Register, then the clock pin is tri-stated when data is not transmitting.
A programmable frame rate divider and a word length divider are used for frame rate sync signal
generation.
Figure 30-4 on page 30-5 shows a block diagram of the clock generator for the transmit section. Whether
the serial bit clock is generated internally or derived from an external source depends on the transmit
direction (
30-4
2
S Mode Select bits (I2S_MODE1 and I2S_MODE0) in the SSI
Word Divider
Word Clock
(÷8, ÷10, ÷12, ÷16)
Figure 30-3. SSI Clocking
MC9328MX1 Reference Manual
Frame Divider
Frame Clock
(÷1, to ÷32)
MOTOROLA