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8.2 System Boot Mode Selection
The operational system boot mode of the MC9328MX1 upon system reset is determined by the
configuration of the four external input pins BOOT[3:0]. The settings of these pins control the following
functions:
•
CS0 boot function of the EIM module
•
Control of the SyncFlash chip select (CSD1) boot function of the SDRAM controller
The settings of the system control module for the system boot mode selection are displayed in Table 8-6.
The MC9328MX1 always begins fetching instructions from address 0x00000000 after reset. The
BOOT[3:0] pins control the memory region that is mapped to address 0x0. The boot modes are defined in
Table 8-6. The BOOT[3:0] pins also control the initial configuration (for example bus width) for the
external memory regions. When an external chip select is enabled by the BOOT[3:0] pins, the first
1 Mbyte range (0x0000000–0x000FFFFF) of the chip select's memory space is also mapped to
address 0x0.
For example, by setting BOOT[3:0] to 0110, the MC9328MX1 will boot from the CS0 memory region
using a 32-bit data bus width. The first 1 Mbyte of the CS0 memory space (0x10000000–0x100FFFFF)
will be mapped to addresses 0x00000000–0x000FFFFF.
The BOOT pins must not change once the MC9328MX1 is out of reset.
Also BOOT[3] must always be tied to VSS.
If Bootstrap ROM is not selected for the boot mode, the internal ROM is
not accessible.
MOTOROLA
NOTE:
NOTE:
Table 8-6. System Boot Mode Selection
Inputs
Output Signals
BOOT[3:0]
Active Device
0000
Bootstrap ROM
0001
16-bit SyncFlash D[15:0]
0010
32-bit SyncFlash
0011
8-bit CS0 at D[7:0]
0100
16-bit CS0 at D[31:16]
0101
16-bit CS0 at D[15:0]
0110
32-bit CS0 at D[31:0]
0111
System Control
System Boot Mode Selection
Reserved
8-7
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