Mma Dct/Idct Registers; Dct/Idct Control Register; Table 17-24 Dct/Idct Control Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Multimedia Accelerator (MMA)

17.3.5 MMA DCT/iDCT Registers

There are 11 registers that control DCT/iDCT functions.

17.3.5.1 DCT/iDCT Control Register

This register controls the function of DCT/iDCT and the interface module. This is a read/write register.
MMA_DCTCTRL
BIT 31 30 29
TYPE r r
0 0 0
RESET
BIT 15 14 13
DCT_HWORD_SWAP
TYPE r r rw
0 0 0
RESET
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–14
DCT_HWORD DCT Half-Word Swap—This bit determines if the
_SWAP data is swapped in half-word (16-bit) or word (32-bit).
Bit 13
DATAINSHIFT DATAINSHIFT—Reserved for future use and should be written with 0 for normal operation.
Bits 12–9
SEMAEN SEMAEN—Reserved for future use and must be written with 0 for normal operation.
Bit 8
DCTXPOSE DCT Transpose—Enables/Disables the DCT output
Bit 7 to be transposed.
DCTCLKEN DCT Clock Enable—Enables/Disables the DCT
Bit 6 clock to save power when DCT is not in use.
SWRST Software Reset—Resets the DCT Module.
Bit 5
DCTBYPASS DCT Bypass—Enables DCT/iDCT input data to be
Bit 4 bypassed to the output without being transformed.
17-24
DCT/iDCT Control Register
28 27 26 25
r r r r r
0 0 0 0
12 11 10 9
DATAINSHIFT
rw rw rw rw
0 0 0 0
Table 17-24. DCT/iDCT Control Register Description
Description
MC9328MX1 Reference Manual
24 23 22 21
r r r r
0 0 0 0
0x0000
8 7 6 5
DCT
SEMA DCT SW
CLK
EN XPOSE RST
EN
rw rw rw rw
0 0 0 0
0x0000
0 = Not swap data in half word, result in
data{data[31:0]}
1 = Swap data in half word
data{data[15:0], data[31:16]
0 = Disable transpose
1 = Enable transpose
0 = Disable clock
1 = Enable clock
0 = No effect
1 = Resets DCT module
0 = Perform transform
1 = Bypass
0x00222400
20 19 18 17
r r r r
0 0 0 0
4 3 2 1
DCT
ARMMCM DCT/
BY DCT ENA
SEL IDCT
PASS
rw rw rw rw
0 0 0 0
Setting
MOTOROLA
Addr
16
r
0
0
rw
0