Motorola DragonBall MC9328MX1 Reference Manual page 960

SDCTLx register
CLKST field, 24-12
COL field, 24-10
DSIZ field, 24-11
IAM bit, 24-11
ROW field, 24-10
SCL field, 24-12
SDE bit, 24-9
SMODE field, 24-9
SP bit, 24-10
SRC field, 24-12
SRCD field, 24-12
SREFR field, 24-11
SRP bit, 24-12
SDHC
card clock control, 20-13
SDI bit, 25-34
SDIM bit, 25-34
SDRAM
memory refresh, 24-65
SDRAM 0 control register, see SDCTL0 register
SDRAM 1 control register, see SDCTL1 register
SDRAM control registers, 24-9
SDRAM memory controller, see SDRAMC
SDRAM operation, 24-37
SDRAM reset register, see SDRST register
SDRAM/SyncFlash command encoding, 24-18
SDRAMC
address multiplexing, 24-29
auto-refresh mode, 24-24
bank addresses, 24-32
block diagram, 24-2
clock suspend low power mode, 24-35
column address strobe, 24-7
command controller, 24-3
configuration registers, 24-3
configuring controller for memory array, 24-37
data aligner/multiplexer, 24-3
data bus (internal), 24-6
data qualifier mask, 24-6
features, 24-1
functional overview, 24-3
general operation, 24-28
memory configuration examples, 24-39
miscellaneous register, see miscellaneous register
mode register programming example, 24-61
multiplexed address bus, 24-6
non-multiplexed address bus, 24-6
normal read/write mode, 24-19
operating modes, 24-18
page and bank address comparators, 24-3
pin configuration, 24-7
powerdown operation in reset and low-power
modes, 24-33
Index-xviii
powerdown timer, 24-4
powerdown, 24-35
precharge command mode, 24-23
programming example
programming model 24-8
refresh request counter, 24-3
refreshing SDRAM, 24-32
reset initialization, 24-56
reset/powerdown, 24-7
row address strobe, 24-6
row/column address multiplexer, 24-3
SDCLK SDRAM clock, 24-5
SDRAM chip select, 24-5
SDRAM clock enable, 24-5
SDRAM selection, 24-37
self-refresh during low power mode, 24-33
self-refresh, 24-33
set mode register mode, 24-25
syncflash
syncflash load command mode, 24-26
syncflash programming, 24-27
write enable, 24-6
SDRST register
RST field, 24-16
SDRST register, 24-16
SECONDS register
SECONDS field, 23-6
SECONDS register, 23-6
SEMAEN bit, 17-24
SFCSR register, 30-31
Sharp configuration 1 register, see LSCR1 register
SIDR register
SID field, 8-2
SIDR register, 8-2
Silicon ID register, see SIDR register
SiliconWave
THRESHOLD register, THRESHOLD field, 16-58
SIM
Clock generation, 25-2
Functional description, 25-4
MC9328MX1 Reference Manual
mode register
bit assignments, 24-63
converting to an address, 24-62
example 1, 24-61
example 2, 24-63
booting from, 24-66
clock suspend timer, 24-69
configuration, 24-66
deep powerdown operation, 24-70
mode register programming, 24-66
operation, 24-65
powerdown operation, 24-70
programming, 24-68
reset initialization, 24-65
,
25-4
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