Receiving Packets; Programming The Fifo Controller - Motorola DragonBall MC9328MX1 Reference Manual

USB Device Port
2. When the FIFO byte count has dropped below the alarm level, a DMA request is generated.
The DMA writes data to the FIFO until the DMA request deasserts.
3. For an N byte packet, the first N-1 bytes are written to the FIFO data register
(USB_EPn_FDAT) as bytes, words, or long words.
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4. On the N byte, to signal the end of a frame, the DMA controller signals to the USB that it
is writing the final byte of the USB_EPn_FDAT register. The last byte in the transfer gets
the end-of-frame tag (bits 31–24 for byte, bits 23–16 for word, and bits 7–0 for longword).
In a double-buffered system, the FIFO depth is twice the size of the USB packet size. Program the FIFO
alarm level to be the same as a single packet. This causes the DMA request to assert whenever there is the
equivalent to one packet of data or less in the FIFO. The system can write data until the DMA request
deasserts, as long as the last byte of each USB packet is tagged as the end-of-frame.

28.7.1.3 Receiving Packets

Perform the following steps to receive a packet of data from the USB host using programmed I/O.
1. Monitor the EOF interrupt for the endpoint.
2. On receiving the EOF interrupt, prepare to read a complete packet of data. Clear the EOF
interrupt so that software receives notification of the next frame.
3. Read the USB_EPn_FDAT register for the next piece of data.
4. Read the USB_EPn_FSTAT register to get the end-of-frame status bits (see note below).
When the end-of-frame bit is set for the current transfer, stop reading data.
5. Go to step 3.
When reading end-of-frame indicators from USB_EPn_FSTAT, the
USB_EPn_FSTAT (FRAME [3:0]) field contains valid frame byte lanes
used on the bus (31:24, 23:16, 15:8, 7:0). Currently, more than one bit can
be set when there are multiple end-of-frame bytes on word or longword
transfers. Extra software might be required to determine the first valid
end-of-frame maker. The value of this field is computed directly from the
frame boundary bits stored in the RAM. The user must ensure that the
RAM data is valid when accessing these bits. For example, when there are
only two bytes of data marked EOF in the RAM, and the user does a
longword access, bits 1:0 of this field are undefined.

28.7.1.4 Programming the FIFO Controller

The FIFO controller has two modes of operation, Frame and Non-Frame. Only Frame mode is normally
used for the USB application.
In Frame mode, the FIFO controller can handle automatic hardware retry of bad packets. During device
initialization, the user configures the FIFOs through the USB_EPn_FCTRL register for FRAME mode.
Data flow is controlled with the end-of-frame and end-of-transfer interrupts, or with the DMA request
lines. For isochronous endpoints, no data retries are performed.
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