Table 15-6 Asp Module Register Memory Map; Programming Model - Motorola DragonBall MC9328MX1 Reference Manual

Analog Signal Processor (ASP)
Auto calibration mode is enabled by setting the ACAL bit and it works only in auto ZXY mode. The
switch settings for X are changed from C6 to CC; and Y is changed from 39 to 33. This connects the ADC
+ve input to QVDD; while the ADC -ve input is connected to GND. This results in a differential input
voltage equal to QVDD, which is fixed using an external regulator.
The Software calibration loop involves three steps:
1. At the beginning of panel calibration routine, enable auto ZXY + auto-calibration mode and
get samples for X and Y. Store the AZ corrected samples in memory for use as a principle
reference. Then disable the auto calibration mode and return to normal modes for sampling.
2. Every time a pen down condition is detected, or at regular time intervals, repeat step 1 to
get an updated reference sample for X and Y. Compare the sample value with the principle
reference taken in step 1 to determine the percentage change.
3. During normal sampling, apply the calculated percentage changes to AZ corrected samples.
This will compensate for the effect of temperature drift on the ADC gain.

15.5 Programming Model

The ASP module includes eight 32-bit registers. Table 15-6 summarizes these registers and their
addresses.
Pen A/D Sample Rate Control Register
Interrupt/Error Status Register
15-8
Table 15-6. ASP Module Register Memory Map
Description
ASP Control Register
Compare Control Register
Interrupt Control Register
Pen Sample FIFO
Clock Divide Register
ASP FIFO Pointer Register
MC9328MX1 Reference Manual
Name Address
ASP_ACNTLCR 0x00215010
ASP_PSMPLRG 0x00215014
ASP_CMPCNTL 0x00215030
ASP_ICNTLR 0x00215018
ASP_ISTATR 0x0021501C
ASP_PADFIFO 0x00215000
ASP_CLKDIV 0x0021502C
ASP_FIFO_PTR 0x00215034
MOTOROLA