Mma Mac Y Count Register; Table 17-22 Mma Mac Y Increment Register Description; Table 17-23 Mma Mac Y Count Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Table 17-22. MMA MAC Y Increment Register Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
YINCR Y Increment—Determines the size of the increment to the MMA_MAC_YINDEX register after each
Bits 15–0 (MMA_MAC_YCOUNT+1) iteration.

17.3.4.6 MMA MAC Y Count Register

MMA_MAC_YCOUNT
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE rw rw rw
0 0 0
RESET
Table 17-23. MMA MAC Y Count Register Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
YCOUNT Y Count—Determines the number of iterations required to:
Bits 15–0 • reload the YDAC Address Index with [MMA_MAC_YBASE + MMA_MAC_YINDEX] (when
the Y INDEX LOAD bit is set)
or,
• increment MMA_MAC_YINDEX by the value in MMA_MAC_YINCR (when the
Y INDEX INCR bit is set). The value written to this register is the actual value minus 1
(0x0003 for four iterations).
MOTOROLA
MMA MAC Y Count Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
YCOUNT
rw rw rw rw
0 0 0 0
Multimedia Accelerator (MMA)
Description
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
rw rw rw rw rw
0 0 0 0 0
0x0000
Description
Programming Model
Addr
0x00222314
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
rw rw rw rw
0 0 0 0
17-23