Dct/Idct Version Register; Table 17-25 Dct/Idct Version Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Table 17-24. DCT/iDCT Control Register Description (Continued)
Name
ARMMCMSEL ARM/Memory Controller Select—Controls
Bits 3–2 DCT/iDCT module data input and output.
DCT/IDCT DCT/IDCT—Selects either DCT or iDCT.
Bit 1
DCT ENA DCT Enable—Enables/Disables the DCT/iDCT.
Bit 0 If data is accessed through the memory controller,
DCT ENA is reset to zero after an 8
completed.

17.3.5.2 DCT/iDCT Version Register

MMA_DCTVERSION
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
RESET
Name
VERSION NUMBER Version Number—Contains the version number of the DCT/iDCT block.
Bits 31–0
MOTOROLA
Description
DCT/iDCT Version Register
28 27 26 25
r r r
0 0 0 0
12 11 10 9
r r r
Table 17-25. DCT/iDCT Version Register Description
Multimedia Accelerator (MMA)
00 = Data in and out through memory
01 = Data in through memory controller
10 = Data in through ARM9 core and out
11 = Data in and out through ARM9 core.
0 = iDCT
1 = DCT
0 = DCT disabled
1 = DCT enabled
×
8 transform is
24 23 22 21
VERSION NUMBER
r r r r r
0 0 0 0
0x0000
8 7 6 5
VERSION NUMBER
r r r r r
0x0000
Description
Programming Model
Setting
controller
and out through ARM9 core.
through memory controller.
0x00222404
20 19 18 17
r r r r
0 0 0 0
4 3 2 1
r r r r
Addr
16
r
0
0
r
17-25