Motorola DragonBall MC9328MX1 Reference Manual page 879

Table 30-12. SSI Receive Configuration Register Description (Continued)
Name
RIE Receive Interrupt Enable—Enables/Disables the receive interrupt
Bit 8 when certain conditions are met. The RIE bit works with the RE bit in
the SCSR.
When the receive FIFO is enabled and the RIE and RE bits are both
set, an interrupt occurs when the RFF bit in the SCSR is set.
When the receive FIFO is disabled and the RIE and RE bits are both
set, an interrupt occurs when the RDR bit in the SCSR is set.
Two receive data interrupts with separate interrupt vectors are
available, Receive Data with Exception and Receive Data Without
Exception. Table 30-13 on page 30-26 shows the conditions that
generate these interrupts and lists the interrupt vectors.
RFEN Receive FIFO Enable—Enables/Disables the receive FIFO. When
Bit 7 the receive FIFO is enabled, a maximum of 8 values can be received
by the SSI without losing data. A ninth value can be received into the
RXSR, however it is not transferred to the receive FIFO. When the
receive FIFO is disabled, only one value can be received into the SRX
register (that value must be read out before another value can be
transferred in from the RXSR).
RFDIR Receive Frame Direction—Selects the direction and source of the
Bit 6 receive frame sync signal. When the RFDIR bit is set, the frame sync
is generated internally and output to the SSI_RXFS pin (if not
configured as a GPIO). When the RFDIR bit is cleared, the receive
frame sync is supplied from an external source.
RXDIR Receive Direction—Selects the direction and source of the clock
Bit 5 signal that clocks the RXSR. When the RXDIR bit is set, the clock is
generated internally and output to the SSI_RXCLK pin (if not
configured as a GPIO). When the RXDIR bit is cleared, the internal
clock generator is disconnected from the SSI_RXCLK pin so an
external clock source can drive this pin to clock the RXSR.
Table 30-14 on page 30-26 shows the clock pin configuration.
RSHFD Receive Shift Direction—Controls whether the MSB or LSB is
Bit 4 received first.
Note: The codec device labels the MSB as bit 0, whereas the
MC9328MX1 labels the LSB as bit 0. When using a standard codec,
the MC9328MX1 MSB (or codec bit 0) is shifted in first, and the
RSHFD bit is cleared.
RSCKP Receive Clock Polarity—Controls the bit clock edge that latches in
Bit 3 data.
RFSI Receive Frame Sync Invert—Selects the logic of the receive frame
Bit 2 sync I/O.
RFSL Receive Frame Sync Length—Selects the length of the frame sync
Bit 1 signal to be generated or recognized. When the word-long frame sync
is selected, this frame sync length is determined by the WL field of the
SRCCR.
MOTOROLA
Description
Synchronous Serial Interface (SSI)
Programming Model
Settings
0 = Disable transmit interrupt
1 = Enable transmit interrupt
0 = Disable receive FIFO
1 = Enable transmit FIFO
0 = Receive frame sync
generated externally
1 = Receive frame sync
generated internally
0 = External source drives
SSI_RXCLK pin
1 = Clock generated
internally and output to
SSI_RXCLK pin
0 = MSB received first
1 = LSB received first
0 = Falling edge of clock
latches data in
1 = Rising edge of clock
latches data in
0 = Active high
1 = Active low
0 = Frame sync is 1 word
long
1 = Frame sync is 1 bit-clock
long
30-25