Motorola DragonBall MC9328MX1 Reference Manual page 948

DMA burst time-out control register,
see DBTOCR register
DMA burst time-out status register,
see DBTOSR register
DMA control register, see DCR register
DMA control register, see DMACR register
DMA interrupt mask register, see DIMR register
DMA interrupt status register, see DISR register
DMA request time-out status register,
see DRTOSR register
DMA transfer error status register, see DSESR register
DMAC
2D memory registers (A & B), 13-16
big endian/little endian byte-ordering, 13-4
block diagram, 13-2
channel registers, 13-18
DMA request table, 13-29
features, 13-1
general registers, 13-8
programming model, 13-4
signal description, 13-3
DMACR register
BURST bit, 19-34
HM field, 19-34
TM field, 19-34
DMACR register, 19-34
DMAREG1 register, 18-14
DMAREG2 register, 18-14
DMAREGx register
RFDEN bit, 18-14
RHDEN bit, 18-14
RHDMA bit, 18-15
TEDEN bit, 18-14
TEDMA bit, 18-14
THDEN bit, 18-14
THDMA bit, 18-14
DODEN bit, 17-26
DOIEN bit, 17-26
DOUTINTR bit, 17-27
DR_A register, 32-16
DR_B register, 32-16
DR_C register, 32-16
DR_D register, 32-16
DR_x register
DR field, 32-16
DRAM reset, see RESET_DRAM signal
DRTOSR register
bits CH10 through CH0, 13-12
DRTOSR register, 13-12
DSESR register
bits CH10 through CH0, 13-13
DSESR register, 13-13
DTR edge triggered interrupt, 27-7
Index-vi
E
Early transmit complete, see ETC bit
EIM
address bus, 11-1
burst mode signals, 11-3
chip select outputs, 11-2
control signals, 11-2
data bus, 11-1
I O signals, 11-1
overview, 11-1
pin configuration, 11-3
programming model, 11-10
read and write signals, 11-2
system connections, typical, 11-6
EIM configuration register, see EIM register
EIM functionality
burst clock divisor, 11-8
burst clock start, 11-9
burst mode operation, 11-8
configurable bus sizing, 11-8
error conditions, 11-9
page mode emulation, 11-9
programmable output generation, 11-8
EIM register, 11-21
Embedded trace macrocell, see ETM
ENABLE register, 25-26
ENCRYPTION_CONTROL_X13 register
ENCRYPT field, 16-42
ENCRYPTION_CONTROL_X13 register, 16-42
Endpointx data register, see USB_EPx_FDAT register
Endpointx FIFO alarm register,
see USB_EPx_FALRM register
Endpointx FIFO write pointer register,
see USB_EPx_FWRP register
Endpointx interrupt mask register,
see USB_EPx_MASK register
Endpointx interrupt status register,
see USB_EPx_INTR register
Endpointx last read frame pointer register,
see USB_EPx_LRFP register
Endpointx last write frame pointer register,
see USB_EPx_LWFP register
EndpointxFIFO read pointer register,
see USB_EPx_FRDP register,
EndpointxFIFO status register,
see USB_EPx_FSTAT register
ENNUM field, 10-10
ERR INTR bit, 17-27
ERRINTREN bit, 17-26
Estimated count register,
see ESTIMATED_COUNT register
ESTIMATED_CLK_HIGH register, 16-37
ESTIMATED_CLK_LOW register, 16-36
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