Clock Synchronization; Figure 29-3 Repeated Start; Figure 29-4 Synchronized Clock Scl - Motorola DragonBall MC9328MX1 Reference Manual

2
I C Module
A master can generate a STOP even when the slave sent an acknowledge.
The slave must release the bus.
Repeated START (H)—Instead of sending a STOP signal, the master can repeat the START signal
•
and the rest of the communication protocol. When a START signal is generated without a preceding
STOP signal, a repeated START occurs. This is shown in Figure 29-3. The master generates a
repeated START to communicate with another slave or with the same slave in a different mode
(transmit/receive mode) without releasing the bus.
MSB
SCL
1 2 3 4
SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Calling Address
START
Signal

29.4.1 Clock Synchronization

When multiple devices simultaneously request the bus, the bus clock is determined by a synchronization
procedure in which the clock lines from the individual devices are compared. The system clock line (SCL)
is the result of an AND operation on all individual clock lines.
After the master drives the SCL low, the internal clocks begin counting their low periods. By performing
an AND operation, the system clock stays low until ALL of the individual device clocks on the bus have
transitioned to the high state. At this point, the individual clocks begin counting their high periods. The
system clock remains high until ANY of the device clocks on the bus transition to the low state.
As a result, the devices with the longest low periods and shortest high periods control the SCL.
Devices with shorter low periods transition to high before the SCL transitions. This wait is shown in
Figure 29-4.
SCL1
SCL2
SCL
29-4
NOTE:
LSB
5 6 7 8 9
XX
Repeated
R/W ACK
START
Bit
Signal H
Figure 29-3. Repeated START
Internal Counter Reset
Figure 29-4. Synchronized Clock SCL
MC9328MX1 Reference Manual
MSB
1 2 3 4 5
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
New Calling Address
Wait Begin Counting High Period
LSB
6 7 8 9
STOP
No
Signal
ACK
Bit
MOTOROLA