Reset Operation - Motorola DragonBall MC9328MX1 Reference Manual

The detection of INT from the Memory Stick occurs in following conditions:
1. MC9328MX1 is in Normal operation mode or Doze mode and the MSHC module is enabled
(MSCEN bit is set).
2. Under condition 1, the MSHC module is in Normal operation mode (PWS bit = 0).
3. The MSHC module recognizes INT when the SDIO remains high for 3 SCLK cycles during
BS0.

21.5.4 Reset Operation

The Memory Stick Control/Status Register's RST bit (MSCS [RST]) provides a mechanism for software
resets. When 1 is written to the RST bit, the MSHC module is reset and an associated I/O reset is initiated.
A value of is maintained for the RST bit for more than SCLK 2 clocks and then must be returned to 0 to
1
perform reset in synchronization with the clock.
A reset of the MSHC module results in:
1. Register operation (Status after RST = 1 and immediately after RST = 0)
— Memory Stick Command Register (MSCMD) = 0x0000
— Memory Stick Control/Status Register (MSCS) = 0x050A
— Memory Stick Receive FIFO Data Register (MSRDATA) and Memory Stick Transmit FIFO
Data Register (MSTDATA) = 0x0000
— Memory Stick Interrupt Control/Status Register (MSICS) = 0x0080
— Memory Stick Parallel Port Control/Data Register (MSPPCD) = 0x0000
— Memory Stick Control 2 Register (MSC2) = ACD, RED and LEND bit = 0. MSCEN bit is not
changed
— Memory Stick Auto Command Register (MSACD) = 0x7001
— Memory Stick FIFO Access Error Control/Status Register (MSFAECS) = 0x0000
— Memory Stick Serial Clock Divider Register (MSCLKD) = no change
— Memory Stick DMA Request Control Register (MSDRQC) = 0x0000
2. Output signal status
— MS_BS —> Low level
— MS_SDIO_OUT —> Low level
— MS_SCLK —> Low level
3. Internal operation
— Internal Interrupt Request signal (MSIRQ) —> High level (Negated)
— Internal DMA Request signal —> High level (Negated)
— The Transmit/Receive FIFOs are cleared
4. The executing protocol is terminated
MOTOROLA Memory Stick Host Controller (MSHC) Module
Memory Stick Host Controller Operation
21-7