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Chapter 17
Multimedia Accelerator (MMA)
17.1 Introduction
Many digital signal processing algorithms require iterative operations that can be closely pipelined,
however they require irregular addressing for data access. These algorithms include FIR filtering,
correlation, and FFT operations. In many system implementations, these operations account for a large
percentage of the total processing cycles.
The multimedia accelerator (MMA) provides the MC9328MX1 with digital signal processing capability
while maintaining efficient utilization of system and bus resources. The MMA in conjunction with the
ARM9 processor core (ARM920T processor), form a hybrid operating environment that combines the
efficiency and simplicity of a RISC processor with the powerful, number crunching, iterative operations of
a digital signal processor. The RISC processor implements the algorithms and processes, assisted by the
MMA in crucial digital signal processing operations. Applications include MPEG or MP3
encoding/decoding and speech compression/decompression such as G.723.1, CELP, or RPE-LTP for
GSM.
17.2 MMA Operation
The MMA module consists of two major blocks—a multiply-accumulate (MAC) block and a discrete
cosine transform (DCT) block. Each of these blocks has its own set of control registers. The control
registers are accessed by the ARM920T processor for configuration as well as data input and result access.
The ARM920T processor enables the signal processing functions in the MMA, which then automatically
issues data access requests to the MC9328MX1's embedded SRAM (eSRAM) through the memory
controller to perform the required functions. The MMA can read from or write to the eSRAM. Output data
is stored in the internal FIFO of the MMA. If the FIFO is not cleared, MMA processes halt so that no
output data is overwritten or lost.
17.2.1 Memory Access
The MMA supports only 32–bit access to its registers because the bus interface to the system bus, referred
to as the Advanced High-performance Bus (AHB), is 32 bits wide. Because the MMA processes data that
is 24 bits wide, access to memory is always in 32–bit words. The MMA supports both big endian and little
endian access.
The MMA's access to the eSRAM is shared with the liquid crystal display controller (LCDC) and the
ARM920T processor. LCDC access to the eSRAM has the highest priority, followed by ARM920T
processor access, and finally MMA access. For this reason, data access latency of the MMA to the eSRAM
can be as long as the LCDC data burst access.
MOTOROLA
Multimedia Accelerator (MMA)
17-1
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