Bank Addresses; Refresh; Figure 24-27 Hardware Refresh Timing Diagram - Motorola DragonBall MC9328MX1 Reference Manual

SDRAM Memory Controller

24.7.1.3 Bank Addresses

Which bank addresses of the SDRAM controller are multiplexed with which MC9328MX1 address pins,
depends on whether or not the memory system is in interleaved mode. For non-interleaved mode, the
SDRAM controller bank addresses SDBA[4:0] are multiplexed with the address pins A[15:11]. For
interleaved mode, the SDRAM controller "interleaved" bank addresses SDIBA[3:0] are multiplexed with
the MC9328MX1 address pins A[19:16]. Instead of detailing the complexity of how these bank addresses
are multiplexed with the corresponding MC9328MX1 address pins with different memory configurations,
the user is directed to Table 24-14. This table explicitly shows which SDRAM memory bank address pin
must be connected to which corresponding MC9328MX1 address pins given different the JEDEC standard
memory configurations. Also, if the user wants to derive how the density of the memory is calculated or
how to derive the page size, they use the following equations:
Page Size (Bytes) = 2
Density (Bytes) = 2

24.7.2 Refresh

SDRAM Controller hardware satisfies all SDRAM refresh requirements after an initial configuration by
the user software. 0, 1, 2, or 4 refresh cycles are scheduled at 31.25 µS (nominal 32 kHz clock) intervals,
providing 0, 2048, 4096, or 8192 refresh cycles every 64 ms. The refresh rate is programmed through the
SREFR field in the SDCTLx registers. Each array can have a different rate, allowing a mix of different
density SDRAMs. Refresh is disabled by hardware reset.
A refresh request is made pending at each rising edge on the 32 kHz clock. In response to this request, the
hardware gains control of the SDRAM as soon as any in-process bus cycle completes. Once it has gained
control of the memory, commands are issued to precharge all banks. Following a row precharge delay
(t ), an auto-refresh command is issued. At t
RP
the specified number of cycles have been run. Figure 24-27 illustrates a 2 refresh sequence.
Burst transfers in progress when the refresh request arrives are allowed to complete prior to the refresh
operation. SDRAM bus accesses queued after the refresh request are held off until the refresh completes.
In Figure 24-28, an access is queued just as the refresh begins. This cycle is delayed until the precharge
and single refresh (SREFR = 01) cycles are run. Bus cycles targeted to other memory or peripheral devices
are allowed to progress normally while the refresh is in progress. None of the pins shared between the
SDRAM and other devices are required for the refresh operation.
32KHz
SDCLK
ADDR
RAS,
CAS,
SDWE
CSDx
DATA
DATA
A
24-32
#Column Address Bits
(# Column Address Bits + # Row Address Bits)
× (Memory Width in Bits / 2)
intervals, additional auto-refresh cycles are issued until
RC
A10 = 1
>= t
RP
PRE-ALL
Figure 24-27. Hardware Refresh Timing Diagram
MC9328MX1 Reference Manual
× (Memory Width in Bits / 8)
>= t
RC
REF A
Eqn. 24-1
Eqn. 24-2
REF A
MOTOROLA