Writing Reentrant Normal Interrupt Routines - Motorola DragonBall MC9328MX1 Reference Manual

Interrupt Controller (AITC)
Table 10-31. Typical Fast Interrupt Entry Sequence (Continued)
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10.5.6 Writing Reentrant Normal Interrupt Routines

The AITC can create a reentrant normal interrupt system. This enables preempting of lower priority level
interrupts by higher priority level interrupts. This requires a small amount of software support and
overhead. The following shows the steps necessary to accomplish this:
1. Push the link register (LR_IRQ) onto the stack (SP_IRQ).
2. Push the saved status register (SPSR_IRQ) onto the stack.
3. Read the current value of NIMASK and push this value onto the stack.
4. Read current priority level via NIVECSR.
5. Interrupts of the equal or lesser priority than the current priority level must be masked via
the NIMASK register by writing value from NIVECSR.
6. Clear the I bit in the ARM920T processor via a MSR / MRS command sequence (a higher
priority normal interrupt can preempt a lower priority one) and change the operating mode
of the ARM920T processor to system mode from IRQ mode.
7. Push the System Mode Link Register (LR) onto the stack (SP_USER).
8. The traditional interrupt service routine is now included.
9. Pop the System Mode Link Register (LR) from the stack (SP_USER).
10. Set the I bit in the ARM920T processor via a MSR/MRS command sequence (disables all
normal interrupts) and change the operating mode of the ARM920T processor to IRQ mode
from system mode.
11. Pop the original value of the normal interrupt mask and write the value to the NIMASK
register.
12. Pop the Saved Status Register from the stack (SP_IRQ).
13. Pop the link register from the stack into the PC.
14. Return from nIRQ.
These steps are still in development and are subject to change. Steps 1, 2,
13, and 14 are automatically done by most C compilers and are included
for completeness.
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