Motorola DragonBall MC9328MX1 Reference Manual page 31

Figure 21-7 Memory Stick Bus Four State Access Protocol . . . . . . . . . . . . . . . . . . . . . . . 21-25
Figure 21-8 Write Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26
Figure 21-9 Read Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26
Figure 21-10 Two State Access Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-28
Figure 21-11 Write Packet Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29
Figure 21-12 Read Packet Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29
Figure 21-13 Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30
Figure 21-14 Bus State Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31
Figure 21-15 SCLK Extension for Data Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31
Figure 22-1 Pulse-Width Modulator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
Figure 22-2 Audio Waveform Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2
Figure 23-1 Real-Time Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
Figure 24-1 SDRAM Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
Figure 24-2 Memory Bank Interleaving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13
Figure 24-3 CAS Latency Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14
Figure 24-4 Precharge Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15
Figure 24-5 Row-to-Column Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15
Figure 24-6 Row Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16
Figure 24-7 Off-Page Single Read Timing Diagram (32-Bit Memory) . . . . . . . . . . . . . . . 24-20
Figure 24-8 On-Page Single Read Timing Diagram (32-Bit Memory) . . . . . . . . . . . . . . . 24-20
Figure 24-9 Off-Page Burst Read Timing Diagram (32-Bit Memory) . . . . . . . . . . . . . . . 24-21
Figure 24-10 On-Page Burst Read Timing Diagram (32-Bit Memory) . . . . . . . . . . . . . . . . 24-21
Figure 24-11 Off-Page Write Followed by On-Page Write Timing Diagram . . . . . . . . . . . 24-21
Figure 24-12 Off-Page Burst Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-22
Figure 24-13 On-Page Burst Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-22
Figure 24-14 Single Write Followed by On-Page Read Timing Diagram . . . . . . . . . . . . . . 24-22
Figure 24-15 Burst Write Followed by On-Page Read Timing Diagram. . . . . . . . . . . . . . . 24-23
Figure 24-16 Single Read Followed by On-Page Write Timing Diagram . . . . . . . . . . . . . . 24-23
Figure 24-17 Burst Read Followed by On-Page Write Timing Diagram. . . . . . . . . . . . . . . 24-23
Figure 24-18 Precharge Bank Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-24
Figure 24-19 Precharge All Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-24
Figure 24-20 Software Initiated Auto-Refresh Timing Diagram . . . . . . . . . . . . . . . . . . . . . 24-25
Figure 24-21 Set Mode Register State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26
Figure 24-22 Set Mode Register Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26
Figure 24-23 Load Command Register Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27
Figure 24-24 SyncFlash Program Mode State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27
Figure 24-25 SyncFlash Program Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28
Figure 24-26 SyncFlash Read Status Register Timing Diagram . . . . . . . . . . . . . . . . . . . . . 24-28
Figure 24-27 Hardware Refresh Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-32
MOTOROLA List of Figures xxxi