Passive Matrix Panel Interface Signals; Figure 19-10 Lcdc Interface Timing For 4-Bit Data Width Gray-Scale Panels - Motorola DragonBall MC9328MX1 Reference Manual

LCD Controller
Pin
PS Primary function of
GPIO Port D [9]
CLS Primary function of
GPIO Port D [8]
REV Primary function of
GPIO Port D [7]

19.3.8.2 Passive Matrix Panel Interface Signals

Figure 19-10 shows the LCD interface timing for monochrome panels and Figure 19-11 shows the LCD
interface timing for passive matrix color panels. Signal polarities are shown positive, however it can be
reversed by clearing the bits in the Panel Configuration Register (PCR). The data bus timing for passive
panels is controlled by the shift clock (LSCLK), line pulse (LP), first line marker (FLM), alternate crystal
direction (ACD), and line data (LD) signals. Operation of the panel interface is accomplished in the
following steps:
1. LSCLK clocks the pixel data into the display driver's internal shift register.
2. LP signifies the end of the current line of serial data and latches the shifted pixel data into
a wide latch.
3. FLM marks the first line of the displayed page. The LD (and the associated LP), enclosed
by the FLM signal, marks the first line of the current frame.
4. ACD toggles after a pre-programmed number of FLM pulses. This signal refreshes the
LCD panel.
The LD bus width is programmable to 1, 2, 4, or 8 bits in monochrome
mode (the COLOR bit in the Panel Configuration register is set to 0). Data
is justified to the least significant bits of the LD [15:0] bus. Passive color
displays use a fixed 2-2/3 pixels of data per 8-bit vector as shown in
Figure 19-11.
FLM
LINE 1
LP
LP
LSCLK
LD0
LD1
LD2
LD3
Figure 19-10. LCDC Interface Timing for 4-bit Data Width Gray-Scale Panels
19-12
Table 19-6. Pin Configuration (Continued)
Setting
1. Clear bit 9 of Port D GPIO In Use Register (GIUS_D)
2. Clear bit 9 of Port D General Purpose Register (GPR_D)
1. Clear bit 8 of Port D GPIO In Use Register (GIUS_D)
2. Clear bit 8 of Port D General Purpose Register (GPR_D)
1. Clear bit 7 of Port D GPIO In Use Register (GIUS_D)
2. Clear bit 7 of Port D General Purpose Register (GPR_D)
LINE 2 LINE 3 LINE 4
1 2 3
[0,0] [0,4] [0,8]
[0,1] [0,5] [0,9]
[0,2] [0,6] [0,10]
[0,3] [0,7] [0,11]
MC9328MX1 Reference Manual
Configuration Procedure
NOTE:
LINE n
59 60
[0,232] [0,236]
[0,233] [0,237]
[0,234] [0,238]
[0,235] [0,239]
LINE 1
m/4-1 m/4
[0,m-8] [0,m-4]
[0,m-7] [0,m-3]
[0,m-6] [0,m-2]
[0,m-5] [0,m-1]
MOTOROLA