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Memory Stick Host Controller (MSHC) Module
Table 21-2. MSHC Module Interrupt Sources Summary (Continued)
Interrupt
MSIRQ Interrupt
Flag Name
Enable Setting(s)
(Register)
FAE (MSICS)
MSICS [INTEN] = 1
MSFAECS [FAEEN] = 1
CRC (MSICS)
MSICS [INTEN] = 1
MSCS [SIEN] = 1
TOE (MSICS)
MSICS [INTEN] = 1
MSCS [SIEN] = 1
MSCS [BSYCNT > 0
1.
DRQ (MSICS):
When DAKEN (MSCS) = 0
DRQ (MSICS) = 1 when Rx FIFO receives at least 1 half-word (RFF = don't care) for receive
DRQ (MSICS) = 1 when Tx FIFO has at least 1 empty slot available (TFE = don't care) for transmit
When DAKEN (MSCS) = 1
DRQ (MSICS) = 1 when Rx FIFO is full (RFF = 1case) for receive
DRQ (MSICS) = 1 when Tx FIFO is empty (TFE = 1 case) for transmit
or
DRQ (MSICS) = 1 when Rx FIFO receives at least 1 half-word (RFF = 0 case) for receive
DRQ (MSICS) = 1 when Tx FIFO has at least 1 empty slot available (TFE = 0 case) for transmit
2.
TPC, means Transfer Protocol Command
3.
PIENx is used for either PIEN0 or PIEN1 bit of the MSPPCD register
21.5.3.2 SDIO Interrupt Operation
An interrupt transfer (INT) state from the Memory Stick to the MSHC module can occur during BS0, as
shown in Figure 21-3.
BS
SDIO
SCLK
Figure 21-3. Memory Stick Interrupt Transfer State (BS0) Operation
When the Memory Stick detects BS0 at the timing indicated by point
state is started at timing indicated at point 3. The MSHC module can terminate MS_SCLKO after the
timing transition indicated by point 3 (MS_SCLKO = low). When an interrupt occurs, it is reflected in the
Memory Stick Interrupt Control/Status Register and SDIO is asserted high (interrupt) by the Memory
Stick. When SDIO = HIGH (INT) is detected during BS0 the INT bit of the Memory Stick Interrupt
Control/Status Register (MSCR) is read and the interrupt status is checked.
21-6
MSIRQ Interrupt
Disable Setting(s)
MSICS [INTEN] = 0
MSICS [INTEN] = 0
MSICS [INTEN] = 0
1
3
2
MC9328MX1 Reference Manual
Interrupt Flag
Read MSFAECS
Write MSCMD
Write MSCMD
BS0
INT
in Figure 21-3, the INT transfer
2
MSIRQ Negate
Clear
Read MSICS
Read MSICS
Read MSICS
7
5
4
6
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