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BYTEx
PCI Interrupt Acknowledge Register
Address
Bit
0 1 2 3 4 5 6 7 8 9
Name
Operation
Reset
PIACK
MPC Slave Address (0,1 and 2) Registers
Address
Bit
0 1 2 3 4 5 6 7 8 9
Name
Operation
Reset
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PCI Byte Enable. This field contains the PCI byte
enables of the PCI transfer in which the error occurred. A
set bit designates a selected byte.
$FEFF0030
1
1
1
1
1
1
0
1
2
3
4
5
PIACK
$00000000
PCI Interrupt Acknowledge. Performing a read from
this register will initiate a single PCI Interrupt
Acknowledge cycle. Any single byte or combination of
bytes may be read from, and the actual byte enable pattern
used during the read will be passed on to the PCI bus.
Upon completion of the PCI interrupt acknowledge cycle,
the Raven will present the resulting vector information
obtained from the PCI bus as read data.
MSADD0 - $FEFF0040
MSADD1 - $FEFF0048
MSADD2 - $FEFF0050
1
1
1
1
1
1
0
1
2
3
4
5
MSADDx
START
R/W
$0000
1
1
1
1
2
2
2
2
2
6
7
8
9
0
1
2
3
4
R
1
1
1
1
2
2
2
2
2
6
7
8
9
0
1
2
3
4
END
R/W
$0000
Registers
2
2
2
2
2
3
3
5
6
7
8
9
0
1
2
2
2
2
2
3
3
5
6
7
8
9
0
1
2-43
2
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