Native Clock High Register; Table 16-20 Native Clock High Register Description - Motorola DragonBall MC9328MX1 Reference Manual

16.5.2.5 Native Clock High Register

The Native Clock High Register concatenated with the Native Clock Low Register (see section 16.5.2.4)
comprise the free-running Bluetooth NATIVECLK. The Native Clock High Register contains the 12 most
significant bits (MSBs) of the 28-bit NATIVECLK.
Writing to the Offset Clock Low Register and the Offset Clock High Register updates ESTIMATEDCLK
with the sum of NATIVECLK and OFFSETCLK on the next NATIVECLK tick.
The Native Clock High Register bits are described in Table 16-20.
NATIVECLK_HIGH
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–12
NATIVECLK_HIGH High Bits of the NATIVECLK—Contains the MSBs (bits 27–16) of the 28-bit NATIVECLK.
Bits 11–0
MOTOROLA
Native Clock High Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
r rw rw rw
0 0 0 0
Table 16-20. Native Clock High Register Description
Bluetooth Accelerator (BTA)
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
NATIVECLK_HIGH
rw rw rw rw rw
0 0 0 0 0
0x0000
Description
Programming Model
Addr
0x0021601C
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
rw rw rw rw
0 0 0 0
16-35