Functional Description; Sim Clock Generator; Baud Clock Generation; Figure 25-2 Sim Clock Generator Diagram - Motorola DragonBall MC9328MX1 Reference Manual

SmartCard Interface Module (SIM)
The SIM also generates 16-bit cyclic redundancy check (CRC) information for both received and
transmitted characters. The CRC portion of the SIM contains a valid CRC detector and a 16-bit CRC
polynomial generator. The SIM CRC section does not generate any interrupts.

25.3 Functional Description

The SIM provides an interface from the MC9328MX1 to one SmartCard. The following subsections
describe the functionality of the SIM.

25.3.1 SIM Clock Generator

The clock generator is responsible for implementing baud rate clock (BAUD_CLK) generation, and
providing clocks to the transmitter, receiver, and port controller sections of the SIM. Figure 25-2 shows a
diagram of the clock generator section. The dividers outlined in bold generate a pulsed clock of the desired
frequency. The pulse is equal in duration to one-half the system clock period.
SCAN_MODE
IPS_CONT_CLK
DIV 2
DIV 4
DIV 8
IPG_CLK
DIV 12
DIV 16
DIV 20
DIV 25
DIV 30
SIM_EN

25.3.1.1 Baud Clock Generation

The clock generator uses one of four different frequencies as a source when generating the baud rate clock.
The default frequency is derived from the clock source of the SmartCard that is selected by the SmartCard
clock select (CLK_SEL) bits in the SIM control (CNTL) register. The output is IPS_CONT_CLK divided
by either 2, 4, 8, 12, 16, 20, 25, or 30 as shown in Section 25.6.2, "Control Register," on page 25-23. The
baud rate generator is the IPS_CONT_CLK input divided by sixteen. The baud rate clock is generated in
two forms in the design. The BAUD_CLK used by the SmartCard is generated so that it is approximately
50% duty at all divide values to meet the requirements of the ISO 7816 specification. The baud_clk that is
used internal to the SIM is generated as a gated version of the IPS_CONT_CLK clock. The resultant clock
is a pulse of one-half IPS_CONT_CLK period in width with the expected frequency.
25-4
CLK_SEL BAUD_SEL
DIV 31
DIV 16
DIV 8
DIV 4
DIV 2
DIV 1
DIVISOR
Reg
Figure 25-2. SIM Clock Generator Diagram
MC9328MX1 Reference Manual
BAUD_CLK
SCEN
RCV_EN
XMT_EN
1
DIV 12
0
DIV 16
BAUD_SEL = 000
SCLK
(50% duty
except
DIV25 with
48% duty)
RCV_CLK
(pulsed)
XMT_CLK
(pulsed)
MOTOROLA