Peripheral Size Registers[1:0] - Motorola DragonBall MC9328MX1 Reference Manual

AHB to IP Bus Interface (AIPI)

7.2.1 Peripheral Size Registers[1:0]

These registers control the size of the IP bus peripheral in each IP bus peripheral location. Peripheral
locations that are not occupied must have their corresponding bits in the PSRs (Peripheral Size Registers)
programmed to 1 in each register.
The least significant bit in the PSRs is a read only bit as it governs the AIPI registers themselves. They are
set and cleared appropriately to indicate the registers are 32 bits. Bits 31 through 16 in both registers are
preset to 1 and the fields are reserved and can only be read.
7.2.1.1 AIPI1 Peripheral Size Register 0 and AIPI2 Peripheral Size Register 0
PSR0_1
PSR0_2
BIT 31 30 29
TYPE
1 1 1
PSR0_1
RESET
1 1 1
PSR0_2
RESET
BIT 15 14 13
TYPE rw rw rw
1 1 1
PSR0_1
RESET
1 1 0
PSR0_2
RESET
Table 7-7. AIPI1 Peripheral Size Register 0 and AIPI2 Peripheral Size Register 0 Description
Name
Reserved Reserved—These bits are reserved and should read 1.
Bits 31–16
MOD_EN_L Module_En (Lower)—Each bit represents the lower bit of
Bits 15–1 the 2-bit field (PSR1 + PSR0) that represents the
Module_En number.
Reserved Reserved—This bit is reserved and should read 0.
Bit 0
7-12
AIPI1 Peripheral Size Register 0
AIPI2 Peripheral Size Register 0
28 27 26 25
1 1 1 1
1 1 1 1
12 11 10 9
MOD_EN_L
rw rw rw rw
1 1 0 0
0 0 1 0
Description
MC9328MX1 Reference Manual
24 23 22 21 20
1 1 1 1 1
0xFFFF
1 1 1 1 1
0xFFFF
8 7 6 5 4
rw rw rw rw rw
0 0 0 0 0
0xF800
0 0 0 0 1
0xC410
See Table 7-9 for bit settings
Addr
0x00200000
0x00210000
19 18 17 16
1 1 1 1
1 1 1 1
3 2 1 0
rw rw rw r
0 0 0 0
0 0 0 0
Settings
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