Interrupt Type Register Low; Normal Interrupt Priority Level Registers; Table 10-11 Interrupt Type Register Low Description - Motorola DragonBall MC9328MX1 Reference Manual

Integrated portable system processor
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10.4.6.2 Interrupt Type Register Low

INTTYPEL
BIT
31
30
29
TYPE
rw
rw
rw
0
0
0
RESET
BIT
15
14
13
TYPE
rw
rw
rw
0
0
0
RESET
Table 10-11. Interrupt Type Register Low Description
Name
INTTYPE
Interrupt Type—Controls whether the individual interrupt
Bits 31–0
sources request a normal interrupt or a fast interrupt.
When a bit is set in INTTYPE and the corresponding interrupt
source is asserted, the interrupt controller asserts a fast
interrupt request.

10.4.7 Normal Interrupt Priority Level Registers

The normal interrupt priority level registers (NIPRIORITY7, NIPRIORITY6, NIPRIORITY5,
NIPRIORITY4, NIPRIORITY3, NIPRIORITY2, NIPRIORITY1, and NIPRIORITY0) provide a software
controllable prioritization of normal interrupts. Normal interrupts with a higher priority level preempt
normal interrupts with a lower priority. The reset state of these registers forces all normal interrupts to the
lowest priority level.
When a level 0 normal interrupt and a level 1 normal interrupt are asserted at the same time, the level 1
normal interrupt is selected assuming that NIMASK has not disabled level 1 normal interrupts. When two
level 1 normal interrupts are asserted at the same time, the level 1 normal interrupt with the highest source
number is selected, also assuming that NIMASK has not disabled level 1 normal interrupts.
These registers are located on the ARM920T processor's native bus, are accessible in 1 cycle, and can be
accessed only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.
MOTOROLA
Interrupt Type Register Low
28
27
26
25
INTTYPE [31:16]
rw
rw
rw
rw
0
0
0
0
12
11
10
9
INTTYPE [15:0]
rw
rw
rw
rw
0
0
0
0
Description
Interrupt Controller (AITC)
24
23
22
21
20
rw
rw
rw
rw
rw
0
0
0
0
0
0x0000
8
7
6
5
4
rw
rw
rw
rw
rw
0
0
0
0
0
0x0000
0 = Interrupt source generates a
1 = Interrupt source generates a
Programming Model
Addr
0x0022301C
19
18
17
16
rw
rw
rw
rw
0
0
0
0
3
2
1
0
rw
rw
rw
rw
0
0
0
0
Settings
normal interrupt (nIRQ)
fast interrupt (nFIQ)
10-15

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