Table 13-17 Channel Control Registers Description - Motorola DragonBall MC9328MX1 Reference Manual

Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–14
DMOD Destination Mode—Selects the destination transfer mode.
Bits 13–12
SMOD Source Mode—Selects the source transfer mode.
Bits 11–10
MDIR Memory Direction—Selects the memory address direction.
Bit 9
MSEL Memory Select—Selects the 2D memory register set when
Bit 8 either source and/or destination is programmed to 2D memory
mode.
DSIZ Destination Size—Selects the destination size of a data
Bits 7–6 transfer.
Note: DSIZ1:DSIZ0 always reads/writes
destination mode is programmed as end-of-burst enable
FIFO, because end-of-burst operation only works for 32-bit
FIFO.
SSIZ Source Size—Selects the source size of data transfer.
Bits 5–4
Note: SSIZ1:SSIZ0 always reads/writes
destination mode is programmed as end-of-burst enable
FIFO, because end of burst operation only works for 32-bit
FIFO.
REN Request Enable—Enables/Disables the DMA request signal.
Bit 3 When REN is set, the DMA burst is initiated by the DMA_REQ
signal from the I/O FIFO. When REN is cleared, DMA transfer
is initiated by CEN.
RPT Repeat—Enables/Disables the data transfer repeat function.
Bit 2 When enabled and when the counter reaches the value set in
Count Register, the Count Register is reset to its zero, an
interrupt is asserted, and the corresponding channel bit in the
Interrupt Mask Register is cleared. The address is reloaded
from the source and destination address register for the next
DMA burst. Data transfer is carried out continuously until the
channel is disabled or it completes the last cycle after RPT is
cleared.
MOTOROLA
Table 13-17. Channel Control Registers Description
Description
DMA Controller
00 = Linear memory
01 = 2D memory
10 = FIFO
11 = End-of-burst enable FIFO
00 = Linear memory
01 = 2D memory
10 = FIFO
11 = End-of-burst enable FIFO
0 = Memory address increment
1 = Memory address decrement
0 = 2D memory register set A
1 = 2D memory register set B
00 = 32-bit destination port
01 = 8-bit destination port
10 = 16-bit destination port
00 when
11 = Reserved
00 = 32-bit source port
01 = 8-bit source port
00 when
10 = 16-bit source port
11 = Reserved
0 = Disables the DMA request
1 = Enables the DMA request signal
0 = Disables repeat function
1 = Enables repeat function
Programming Model
Settings
selected
selected
signal (when the peripheral
asserts a DMA request, no
DMA transfer is triggered);
DMA transfer is initiated by
CEN only
(when the peripheral asserts a
DMA request, a DMA transfer
is triggered)
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