General Description - Motorola DragonBall MC9328MX1 Reference Manual

Chapter 32
GPIO Module and I/O Multiplexer (IOMUX)

32.1 General Description

This chapter describes the four GPIO ports of the MC9328MX1. All of the GPIO port pins are multiplexed
with other signals. See Chapter 2, "Signal Descriptions and Pin Assignments," for detailed I/O
multiplexing information.
This section contains the description of the top level I/O multiplexing strategy in the MC9328MX1, which
consists of two modules:
• Software controllable multiplexing performed in the GPIO module
• Hardware multiplexing performed in the IOMUX module
The I/O multiplexing strategy is designed to configure the inputs and outputs of the MC9328MX1 to allow
the same I/O pad to be used for peripheral functions and GPIO. The I/O multiplexing is designed to be as
flexible as possible and to allow the simple and quick reuse of this system in future derivatives of the
MC9328MX1. In addition to the I/O multiplexing, the IOMUX module contains the JTAG shift registers,
which significantly simplify the I/O design.
There are four GPIO ports on the MC9328MX1: Port A, Port B, Port C, and Port D. Each port consists of
32 pins, however not all pins are used. The usable port pins are:
Port A—pins 0–31
•
Port B—pins 8–31
•
Port C—pins 19-31
•
Port D—pins 6–31
•
Figure 32-1 on page 32-2 depicts a top-level view of the IOMUX and GPIO modules for a single port pin.
This circuitry is duplicated for each of the 110 port pins.
MOTOROLA GPIO Module and I/O Multiplexer (IOMUX) 32-1