Uart Control Register 1; Table 27-14 Uart1 Control Register 1 And Uart2 Control Register 1 Description - Motorola DragonBall MC9328MX1 Reference Manual

27.7.3 UART Control Register 1

The UART Control Register 1s enable the UART and the transmit and receive blocks. They controls the
TxFIFO and RxFIFO levels and enables the TRDY and RRDY interrupts.
UCR1_1
UCR1_2
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TRDY
ADEN ADBR
EN
TYPE rw rw rw
0 0 0
RESET
Table 27-14. UART1 Control Register 1 and UART2 Control Register 1 Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
ADEN Automatic Baud Rate Detection Interrupt
Bit 15 Enable—Enables/Disables the automatic baud rate
detect complete (ADET) bit to generate an interrupt
(UART_MINT_UARTC = 0).
ADBR Automatic Detection of Baud Rate—Enables/Disables
Bit 14 automatic baud rate detection. When the ADBR bit is set
and the ADET bit is cleared, the receiver detects the
incoming baud rate automatically. The ADET flag is set
when the receiver verifies that the incoming baud rate is
detected properly by detecting an ASCII character "A" or
"a" (0x61 or 0x41).
TRDYEN Transmitter Ready Interrupt Enable—Enables/Disables
Bit 13 the transmitter Ready Interrupt (TRDY) when the
transmitter has one or more slots available in the TxFIFO.
The fill level in the TXFIFO at which an interrupt is
generated is controlled by TxTL bits. When TRDYEN is
negated, the transmitter ready interrupt is disabled.
IDEN Idle Condition Detected Interrupt
Bit 12 Enable—Enables/Disables the IDLE bit to generate an
interrupt (UART_MINT_RX = 0).
MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules
UART1 Control Register 1
UART2 Control Register 1
28 27 26 25 24
r r r r r
0 0 0 0 0
12 11 10 9 8
RRDY RDMA
IDEN ICD
EN EN
rw rw rw rw rw
0 0 0 0 0
Description
23 22 21 20
r r r r
0 0 0 0
0x0000
7 6 5 4
TXMPTY RTSD SND
IREN
EN EN BRK
rw rw rw rw
0 0 0 0
0x0004
0 = Disable the automatic baud
1 = Enable the automatic baud
0 = Disable automatic detection of
1 = Enable automatic detection of
0 = Disable the transmitter ready
1 = Enable the transmitter ready
0 = Disable the IDLE bit
1 = Enable the IDLE bit
Programming Model
Addr
0x00206080
0x00207080
19 18 17 16
r r r
0 0 0
3 2 1
TDMA UARTCLK UART
DOZE
EN EN EN
rw rw rw rw
0 1 0
Settings
rate detection interrupt
rate detection interrupt
baud rate
baud rate
interrupt
interrupt
27-25
r
0
0
0