Endpoint N Interrupt Status Registers - Motorola DragonBall MC9328MX1 Reference Manual

USB Device Port
Table 28-14. Endpoint n Status/Control Registers Description (Continued)
Name
Maximum Packet Size —Sets the maximum packet
MAX
size for the endpoint (MAX is ignored for -ronous
Bits 6–5
endpoints).
Note: The maximum packet size cannot be greater
than the endpoint's FIFO size. See Table 28-1 for FIFO
sizes.
TYP Endpoint Type—Sets up the type of endpoint being
Bits 4–3 used. Endpoint 0 is defined as a control endpoint,
however all other endpoints can be any type.
ZLPS Zero Length Packet Send—Determines if a zero
Bit 2 length packet will be sent to the host. If the FIFO is
empty and the USB host requests an IN transaction, the
USB module can send a zero length packet in
response. ZLPS automatically clears after the
transaction completes successfully. ZLPS signifies to
the USB host that the end of data was reached in a data
transmission when the end of data lands on a packet
boundary and there is no short packet to signify the end
of data.
FLUSH Flush—Flushes the associated FIFO to its empty state.
Bit 1
FORCE_STALL Force a Stall Condition—Causes the endpoint to
Bit 0 respond with a STALL to the next poll, and
automatically clears when the stall takes effect.
Note: There is no endpoint stalled indicator because
one is not returned from the UDC. The USB host is
expected to communicate with the USB device through
device requests to fix the stall condition. The USB host
sends a CLEAR_FEATURE request to the UDC module
to clear the stall and resume normal operations.

28.3.11 Endpoint n Interrupt Status Registers

The Endpoint n Interrupt Status Registers monitor the status of a specific endpoint and generates CPU
interrupts each time a monitored event occurs.
When an interrupt is set, it remains set until cleared by writing 1 to the corresponding bit. Interrupts do not
clear automatically when the event that caused them goes away (for example, when reset signaling comes
and goes with no intervention from software, both RESET_START and RESET_STOP are set). Writing 0
has no effect.
If a register write occurs at the same time an interrupt is received, the interrupt takes precedence over the
write.
The number of Endpoint n Interrupt Status Registers in the MC9328MX1 depends on the number of
endpoints configured.
28-20
Description
MC9328MX1 Reference Manual
Settings
00 = Packet is 8 Bytes
01 = Packet is 16 Bytes
10 = Packet is 32 Bytes
11 = Packet is 64 Bytes
00 = Control
01 = Isochronous
10 = Bulk
11 = Interrupt
0 = No zero length packet to send
1 = A zero length packet to send
0 = Do nothing
1 = Initiate flush operation
0 = Do nothing
1 = Force a stall condition
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