Bus State Control Operation; Mshc Module Interrupt Operation; Interrupt Sources; Table 21-2 Mshc Module Interrupt Sources Summary - Motorola DragonBall MC9328MX1 Reference Manual

21.5.2 Bus State Control Operation

The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS,
MS_SDIO, and MS_SCLKO (or MS_SCLKI). Communication is always initiated by the MSHC module
and operates the bus in either four-state or two-state access mode.
The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according
to its attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet
transmissions occur. During the BS1, BS2, and BS3 states, packet communications are executed. The BS1,
BS2, and BS3 states are regarded as one packet length and one communication transfer is always
completed within one packet length (in four-state access mode).
The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When
an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0
and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO.

21.5.3 MSHC Module Interrupt Operation

The MSHC module provides a single interrupt to the interrupt controller. For interrupt pin assignments, see
Chapter 10, "Interrupt Controller (AITC)."

21.5.3.1 Interrupt Sources

The MSHC module provides interrupt source and status flags. Generally, after MSIRQ assertion (when an
interrupt event occurs), there is distinction in the MSHC module about how to clear the interrupt to the
ARM920T processor (MSIRQ negate) and clearing the interrupt condition in the MSHC module (Interrupt
Flag Clear). Table 21-2 summarizes the interrupt sources that assert MSIRQ to the interrupt controller.
Table 21-2. MSHC Module Interrupt Sources Summary
Interrupt
MSIRQ Interrupt
Flag Name
Enable Setting(s)
(Register)
INT (MSCS) MSICS [INTEN] = 1
RDY (MSICS) MSICS [INTEN] = 1
MSCS [SIEN] = 1
SIF (MSICS) MSICS [INTEN] = 1
MSCS [SIEN] = 1
MSC2 [ACD] = 0
1 MSICS [DRQSL] = 1
DRQ (MSICS)
MSICS [INTEN] = 1
PIN (MSICS) MSICS [INTEN] = 1
MSICS [PINEN] = 1
MSPPCD [PIENx]
MOTOROLA
MSIRQ Interrupt
Disable Setting(s)
MSICS [INTEN] = 0
MSICS [INTEN] = 0
MSICS [INTEN] = 0
MSC2 [ACD] = 1
MSICS [INTEN] = 0
MSICS [DRQSL] = 0
MSICS [INTEN] = 0
3
= 1
Memory Stick Host Controller (MSHC) Module
Memory Stick Host Controller Operation
Interrupt Flag
Clear
Read MSICS
Write MSCMD
Write MSCMD
or
Write MSTDATA
or
for Write TPC
Read MSRDATA
for Read TPC
Read MSPPCD
MSIRQ Negate
Depends on
interrupt source
Read MSICS
Read MSICS
Read MSICS
2 or
Write MSTDATA
for Write TPC
Read MSRDATA
for Read TPC
Read MSICS
21-5