Mcu Pll And System Clock Control Register 1; Generation Of 48 Mhz Clocks; Table 12-11 System Pll Multiplier Factor - Motorola DragonBall MC9328MX1 Reference Manual

12.5.3.2 MCU PLL and System Clock Control Register 1

The MCU PLL and System Clock Control Register 1 (MPCTL1) is a 32-bit register that directs the
operation of the on-chip MCU PLL. The MPCTL1 control bits are described in Table 12-10.
MPCTL1 MCU PLL and System Clock Control Register 1
BIT 31 30 29 28
TYPE r r r r
0 0 0 0
RESET
BIT 15 14 13 12
TYPE r r r r
0 0 0 0
RESET
Table 12-10. MCU PLL and System Clock Control Register 1 Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–7
BRMO BRM Order—Controls the BRM order. The first order BRM is used if a
Bit 6 MF fractional part is both more than 1/10 and less than 9/10. In other
cases, the second order BRM is used. The BRMO bit is cleared by a
hardware reset. A delay of reference cycles is required between two write
accesses to BRMO.
Reserved Reserved—These bits are reserved and should read 0.
Bits 5–0

12.5.4 Generation of 48 MHz Clocks

The USB interface clock (CLK48M) is used internally by the USB module. Its frequency is set to 48 MHz
using the PLL control registers assuming a default input clock frequency 16.384 MHz. This input clock
frequency assumes a 32 kHz crystal input.
The predivider/multiplier output depends on the input clock frequency as shown in Table 12-11.
PLL
Input Premultiplier
Frequency
32 kHz 16.384 MHz
The default setting exception is USB_DIV. The user must program this to 010.
MOTOROLA
27 26 25 24 23
r r r r r
0 0 0 0 0
11 10 9 8 7
r r r r r
0 0 0 0 0
Description
Table 12-11. System PLL Multiplier Factor
PD MFD MFI
1 63
Phase-Locked Loop and Clock Controller
22 21
r r
0 0
0x0000
6 5
BRMO
rw r
0 0
0x0000
PLL
MFN Output
Frequency
5 55 96 MHz
Programming Model
Addr
0x0021B008
20 19 18 17 16
r r r r r
0 0 0 0 0
4 3 2 1 0
r r r r r
0 0 0 0 0
Settings
0 = BRM contains
first order
1 = BRM contains
second order
USB
USBDIV Clock
Frequency
2 48 MHz
12-11