Endpoint N Interrupt Mask Registers; Table 28-16 Endpoint N Interrupt Mask Registers Description - Motorola DragonBall MC9328MX1 Reference Manual

28.3.12 Endpoint n Interrupt Mask Registers

The Endpoint n Interrupt Mask Registers allow the user to mask individual interrupts for each endpoint.
Writing 1 to a bit in this register masks the corresponding interrupt in the USB_EPn_STAT register.
Writing 0 unmasks the interrupt.
The number of Endpoint n Interrupt Mask Registers in the MC9328MX1 depends on the number of
endpoints configured.
USB_EP0_MASK
USB_EP1_MASK
USB_EP2_MASK
USB_EP3_MASK
USB_EP4_MASK
USB_EP5_MASK
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Table 28-16. Endpoint n Interrupt Mask Registers Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–9
FIFO_FULL FIFO Full Mask—Enables/Disables the FIFO Full
Bit 8 interrupt.
FIFO_EMPTY FIFO Empty Mask—Enables/Disables the FIFO Empty
Bit 7 interrupt.
FIFO_ERROR FIFO Error Mask—Enables/Disables the FIFO Error
Bit 6 interrupt.
FIFO_HIGH FIFO High Alarm Mask—Enables/Disables the FIFO
Bit 5 High Alarm interrupt.
FIFO_LOW FIFO Low Alarm Mask—Enables/Disables the FIFO Low
Bit 4 Alarm interrupt.
MOTOROLA
Endpoint 0 Interrupt Mask Register
Endpoint 1 Interrupt Mask Register
Endpoint 2 Interrupt Mask Register
Endpoint 3 Interrupt Mask Register
Endpoint 4 Interrupt Mask Register
Endpoint 5 Interrupt Mask Register
28 27 26 25 24
r r r r r
0 0 0 0 0
12 11 10 9 8
FIFO_
FULL
r r r r rw
0 0 0 0 1
Description
USB Device Port
23 22 21
r r r
0 0 0
0x0000
7 6 5
FIFO_ FIFO_ FIFO_ FIFO_
EMPTY ERROR HIGH LOW
rw rw rw
1 1 1
0x01FF
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
Programming Model
Addr
0x00212038
0x00212068
0x00212098
0x002120C8
0x002120F8
0x00212128
20 19 18 17
r r r r
0 0 0 0
4 3 2 1
MDEV DEV
EOT EOF
REQ REQ
rw rw rw rw
1 1 1 1
Settings
28-23
16
r
0
0
rw
1