Generation Of Stop; Generation Of Repeated Start; Slave Mode; Arbitration Lost - Motorola DragonBall MC9328MX1 Reference Manual

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I C Module
When the device is functioning as the addressed slave (the IAAS bit in the I2SR is set), the SRW bit in the
I2SR Register is read to determine the direction of the next transfer, and MTX is programmed accordingly.
For slave-mode data cycles (IAAS = 0), the SRW bit is invalid. The MTX bit is read to determine the
current transfer direction.
The following is an example of a software response by a master transmitter in the interrupt routine (see
Figure 29-5 on page 29-17).

29.7.4 Generation of STOP

A data transfer ends when the master signals a STOP, which can occur after all data is sent. When the
master receiver intends to terminate a data transfer, it must inform the slave transmitter by not
acknowledging the last data byte. This is done by setting the TXAK bit in the I2CR Register before reading
the next-to-last byte. Before the last byte is read, a STOP signal must be generated.

29.7.5 Generation of Repeated START

After the data transfer is complete, the master can retain control of the bus by issuing a repeated START.
Instead of sending a STOP signal, the master sends another START signal and sends out another slave
calling address. See Figure 29-3 on page 29-4 for more information.

29.7.6 Slave Mode

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When another device initiates communication on the bus, the MC9328MX1 I C module must verify
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whether it is addressed as the slave device by checking the I C Addressed as a Slave bit (IAAS) in the
I2SR Register. When IAAS is set, the software reads the SRW bit in the I2SR Register and sets the
Transmit/Receive Mode Select bit (MTX) in the I2CR Register accordingly. Writing to the I2CR Register
clears the IAAS bit automatically. The IAAS bit is set only at the end of the address cycle, even when there
are multiple data bytes transferred.
Initiate a data transfer by writing data to the I2DR Register for slave transmits, or by reading data from the
I2DR Register in slave receive mode. A dummy read of the I2DR Register in slave receive mode releases
the SCL, allowing the master to send data.
In the slave transmitter routine, the Receive Acknowledge bit (RXAK) in the I2SR Register must be tested
before sending the next byte of data. When RXAK is high, the master receiver intends to terminate the data
transfer. The software must switch the MC9328MX1 from transmitter to receiver mode. Reading the I2DR
Register releases the SCL so the master can generate a STOP signal.

29.7.7 Arbitration Lost

When several devices try to engage the bus at the same time, one becomes the master and the hardware
immediately switches the other devices to slave receive mode. Data output to the SDA line stops, however
the serial clock continues to be generated until the end of the byte during which arbitration is lost. An
interrupt occurs at the falling edge of the ninth clock of this transfer.
When a device that is not a master tries to transmit or generate a START, hardware automatically clears
the Master/Slave Mode Select bit (MSTA) in the I2CR Register without signalling a STOP, generates an
interrupt to the ARM920T processor, and sets the Arbitration Lost bit (IAL) in the I2SR Register to
indicate a failed attempt to engage the bus. The slave service routine must first test the IAL bit and clear it
when it is set.
29-16 MC9328MX1 Reference Manual MOTOROLA