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SmartCard Interface Module (SIM)
25.8.1 Receive Parity Errors and Parity NACK Generation
The SIM receiver checks every byte received for proper parity. The IC control bit in the CNTL register
(see page 25-23) controls whether it checks for odd parity or even parity. When checking for odd parity,
the number of logic 1s contained in the 9 received bits (8 data bits and 1 parity bit) should be odd.
Likewise, when checking for even parity, the number of logic 1s contained in the 9 received bits (8 data
bits and 1 parity bit) should be even.
When a parity error is detected on a given byte, the PE bit for that byte is set in the FIFO. The PE flag for
each byte is read out of the FIFO when the data itself is read. There is no need to attempt to clear the parity
error flag in the FIFO. It is simply overwritten the next time a byte is received into that position of the
FIFO. A parity error cannot cause an interrupt.
It is possible for the SIM to automatically request that the SmartCard re-send a byte found to have a parity
error by generating a NACK pulse on the SIM XMT pin. The SIM generates a NACK pulse on a byte
received with a parity error when the ANACK bit in the CNTL register (see page 25-23) is set. Bytes with
parity errors that cause a NACK pulse are still placed into the FIFO just as bytes that do not cause a NACK
pulse are. It is up to the software to discard data bytes with parity errors. As opposed to transmit NACK
generation, there is no way to limit to the number of times a given byte causes a NACK other than to
disable the ANACK bit in the CNTL register.
The ANACK bit in the CNTL register is also used in initial character mode
to enable the retransmission of initial characters in the event that an invalid
initial character is received.
When generating a NACK pulse, the SIM generates the low pulse starting at 10.5 ETUs and lasting for 1
ETU (see Figure 25-5 on page 25-8).
25.8.2 Receive Frame Errors
The SIM receiver checks every byte received for a proper stop bit. A stop bit must exist during at least the
first half of the 11th ETU after the start of the character. When this is not true, a frame error is flagged.
When a frame error is detected on a given byte, the FE bit for that byte is set in the FIFO. The FE flag for
each byte is read out of the FIFO when the data itself is read. There is no need to clear the frame error flag
in the FIFO. It is simply overwritten the next time a byte is received into that position of the FIFO. A frame
error cannot cause an interrupt, nor can it create a NACK pulse to the receiver asking for a retransmission
of the corrupted data.
25.8.3 Receive Overrun Errors and Overrun NACK Generation
When there already exists 32 unread bytes in the FIFO, a received character causes the SIM receiver to flag
an overrun condition. This condition always sets the overrun error flag (OEF) bit in the RCV_STATUS
register (see page 25-29). The received byte is discarded, leaving the 32 unread bytes in the FIFO
unaltered.
It is possible for the SIM to automatically request that the SmartCard re-send the byte that caused the
overrun condition by generating a NACK pulse on the SIM XMT pin. The SIM generates a NACK pulse
for the byte that caused the overrun condition when the control bit ONACK in the CNTL register (see page
25-23) is set. In this case, the existence of an OEF flag does not indicate the loss of data, instead it indicates
a NACK (retransmission request) due to a full Receive FIFO. As opposed to transmit NACK generation,
there is no limit to the number of times an overrun condition may cause a NACK other than to disable
ONACK itself. When generating a NACK pulse, the SIM generates the low pulse starting at 10.5 ETUs
and lasting for 1 ETU (see Figure 25-5 on page 25-8).
25-46
NOTE:
MC9328MX1 Reference Manual
MOTOROLA
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