Watchdog Control Register; Programming Model; Table 14-2 Watchdog Control Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Watchdog Timer Module

14.7 Programming Model

The watchdog timer has three registers in its programming model: Watchdog Control Register (WCR),
Watchdog Service Register (WSR), and Watchdog Status Register (WSTR).
.
Name 15
R 0
WCR
WHA
($00201000)
W
LT
R
WSR
($00201004)
W
R 0
WSTR
($00201008)
W

14.7.1 Watchdog Control Register

The WCR is a 32-bit read/write (byte writable) register. It controls the Watchdog operation. See
Table 14-2 on page 14-6 for bit descriptions and settings.
WCR
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT
15 14 13
WHALT
TYPE rw rw rw
0 0 0
RESET
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits
31–15
WHALT Watchdog Halt—When set, the watchdog counter immediately
Bit 15 stops counting and the counter value is held at the last value.
The WHALT bit can be cleared by writing 0 to it or it can be
automatically cleared by the occurrence of any of three system
events, fast interrupt, slow interrupt, or system reset.
14-6
14 13 12 11 10
WT[6:0]
0 0 0 0 0
Watchdog Control Register
28 27 26 25 24
r r r r
0 0 0 0
12 11 10 9
WT
rw rw rw rw rw
0 0 0 0
Table 14-2. Watchdog Control Register Description
Description
MC9328MX1 Reference Manual
9 8 7 6
0 0
WSR[15:0]
0 TINT 0 0
23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
WIE
r r r rw
0 0 0 0 0
0x0000
0 = Counter is not halted
1 = Counter is halted
5 4 3 2 1
0
WIE TMD SWR WDEC WDE
0 0 0 0 0
0x00201000
19 18 17
r r r
0 0 0
3 2 1
TMD SWR WDEC
rw rw rw
0 0 0
Settings
MOTOROLA
0
TOUT
Addr
16
r
0
0
WDE
rw
0