Uart2 Control Register 3; Table 27-17 Uart1 Control Register 3 And Uart2 Control Register 3 Description - Motorola DragonBall MC9328MX1 Reference Manual

27.7.5.2 UART2 Control Register 3

UCR3_2
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
DTR
DPEC
EN
TYPE rw rw rw
0 0 0
RESET
Table 27-17. UART1 Control Register 3 and UART2 Control Register 3 Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
DPEC DTR Interrupt Edge Control—Controls the edge
Bits 15–14 that generates an interrupt. An interrupt is generated
only if the DTREN bit is set.
DTREN Data Terminal Ready Interrupt Enable—Controls
Bit 13 the DTR edge sensitive interrupt. When DTREN is
asserted and the programmed edge is detected on
the UART2_DTR pin, the DTRF bit is asserted (see
Table 27-4).
PARERREN Parity Error Interrupt Enable—Enables/Disables
Bit 12 the interrupt. When asserted, PARERREN causes
the PARITYERR bit to generate an interrupt
(UART_MINT_PFERR
FRAERREN Frame Error Interrupt Enable—Enables/Disables
Bit 11 the interrupt. When asserted, FRAERREN causes
the FRAMERR bit to generate an interrupt
(UART_MINT_PFERR
DSR Data Set Ready—Selects the logic level for the
Bit 10 UART_DSR pin for the modem interface.
DCD Data Carrier Detect—Selects the logic level for the
Bit 9 UART_DCD pin for the modem interface.
RI Ring Indicator—Selects the logic level for the
Bit 8 UART_RI pin for the modem interface.
MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules
UART2 Control Register 3
28 27 26
r r r
0 0 0
12 11 10
PARERR FRAERR
DSR DCD RI
EN EN
rw rw rw
0 0 0
Description
=
0)
=
0)
25 24 23 22 21
r r r r r
0 0 0 0 0
0x0000
9 8 7 6 5
AIR
RXDS
INT
EN
EN
rw rw r rw rw
0 0 0 0 0
0x0000
00 = Interrupt generated on rising edge
01 = Interrupt generated on falling edge
1X = Interrupt generated on either edge
0 = Disable the data terminal ready
interrupt
1 = Enable the data terminal ready interrupt
0 = Disable the parity error interrupt
1 = Enable the parity error interrupt
0 = Disable the frame error interrupt
1 = Enable the frame error interrupt
0 = The UART_DSR pin is logic 0
1 = The UART_DSR pin is logic 1
0 = The UART_DCD pin is logic 0
1 = The UART_DCD pin is logic 1
0 = The UART_RI pin is logic 0
1 = The UART_RI pin is logic 1
Programming Model
0x00207088
20 19 18 17
r r r r
0 0 0 0
4 3 2 1
AWAK
REF25 REF30 INVT BPEN
EN
rw rw rw rw
0 0 0 0
Settings
Addr
16
r
0
0
rw
0
27-33