Motorola DragonBall MC9328MX1 Reference Manual page 872

Synchronous Serial Interface (SSI)
Table 30-7. SSI Control/Status Register Description (Continued)
Name
TUE Transmitter Underrun Error—Indicates that the TXSR is empty
Bit 4 AND a transmit time slot occurs. The TDE bit in this register
indicates the first condition. When a transmit underrun error
occurs, the data that was in the TXSR is retransmitted.
In normal mode, a transmit time slot occurs when the frame sync
is asserted. In network mode, each time slot requires data
transmission and is a transmit time slot (TE = 1).
When the TUE bit is set, there is no data transferred to the TXSR.
However, the TUE bit does cause a change in the interrupt vector
used for transmit interrupts so that a different interrupt handler
can be used for a transmit underrun condition. When a transmit
interrupt occurs with the TUE bit set, the Transmit Data with
Exception interrupt is generated. When a transmit interrupt
occurs with the TUE bit cleared, the Transmit Data interrupt is
generated.
TUE is cleared by reading this register, and then writing to the
STX register or to the SSI Time Slot Register (STSR).
TFS Transmit Frame Sync—Indicates that a frame sync occurred
Bit 3 during transmission of the last word written to the STX register.
Data written to the STX register during the time slot when the TFS
bit is set is sent during the second time slot (in network mode) or
in the next first time slot (in normal mode). In network mode, the
TFS bit is set during transmission of the first slot of the frame. It is
then cleared when starting transmission of the next slot.
RFS Receive Frame Sync—Indicates that a frame sync occurred
Bit 2 when receiving a word into the SRX register.
In network mode, the RFS bit is set when the first slot of the frame
is being received. It is cleared when the next slot of the frame
begins to be received.
RFF Receive FIFO Full—Indicates that the data level in the receive
Bit 1 FIFO reaches the Receive FIFO Full Water Mark. The Water
Mark is defined in the RFWM field of the SSI FIFO Control/Status
Register (SFCSR). The receive FIFO must be enabled or RFF is
meaningless.
When RFF is set, data can be read from the receive FIFO via the
SRX register. When the RX FIFO has received 8 bytes of data, all
further received data is ignored until the data is read out of the
receive FIFO.
Note: An interrupt is generated only when both the RFF and
RIE bits in the SRCR are set and the receive FIFO (the RFEN bit
in the SRCR) is enabled.
30-18
Description
MC9328MX1 Reference Manual
Settings
0 = TXSR is empty and no
transmit time slot has
occurred OR the TXSR
is not empty
1 = TXSR is empty and a
transmit time slot has
occurred
0 = No frame sync occurred
during transmission
1 = A frame sync occurred
during transmission
0 = No frame sync occurred
when receiving
1 = A frame sync occurred
when receiving
0 = Data level in the receive
FIFO exceeds Water
Mark level
1 = Data level in receive
FIFO reaches Water
Mark
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