Offset Count Register; Table 16-18 Offset Count Register Description - Motorola DragonBall MC9328MX1 Reference Manual

16.5.2.3 Offset Count Register

The Offset Count Register contains a high resolution counter that generates OFFSETCLK by dividing the
8 MHz clock by 2,500 to generate a 3.2 kHz SYSTICK that updates the OFFSETCLK registers. The Offset
Count Register bits are described in Table 16-18.
OFFSET_COUNT
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–12
OFFSET_COUNT Off Set Count—Contains the OFFSETCOUNT, which generates OFFSETCLK.
Bits 11–0
MOTOROLA
Offset Count Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
r rw rw rw
0 0 0 0
Table 16-18. Offset Count Register Description
Bluetooth Accelerator (BTA)
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
OFFSET_COUNT
rw rw rw rw rw
0 0 0 0 0
0x0000
Description
Programming Model
Addr
0x00216014
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
rw rw rw rw
0 0 0 0
16-33