Texas Instruments Chipcon CC2430 Manual
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Texas Instruments Chipcon CC2430 Manual

Texas Instruments Chipcon CC2430 Manual

A true system-on-chip solution for 2.4 ghz ieee 802.15.4 / zigbee
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A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee
Applications
• 2.4 GHz IEEE 802.15.4 systems
®
• ZigBee
systems
• Home/building automation
• Industrial Control and Monitoring
Product Description
CC2430
The
comes in three different flash
versions: CC2430F32/64/128, with 32/64/128
KB of flash memory respectively. The
is a true System-on-Chip (SoC) solution
specifically tailored for IEEE 802.15.4 and
®
ZigBee
applications. It enables ZigBee
nodes to be built with very low total bill-of-
CC2430
material costs. The
excellent performance of the leading
RF transceiver with an industry-standard
enhanced 8051 MCU, 32/64/128 KB flash
memory, 8 KB RAM and many other powerful
features. Combined with the industry leading
®
ZigBee
protocol stack (Z-Stack™) from Texas
CC2430
Instruments, the
most competitive ZigBee
CC2430
The
is highly suited for systems where
ultra low power consumption is required. This
is ensured by various operating modes. Short
transition times between operating modes
further ensure low power consumption.
Key Features
•
RF/Layout
o 2.4 GHz IEEE 802.15.4 compliant RF
transceiver (industry leading CC2420 radio
core)
o Excellent receiver sensitivity and robustness to
interferers
o Very few external components
o Only a single crystal needed for mesh network
systems
o RoHS compliant 7x7mm QLP48 package
•
Low Power
o Low current consumption (RX: 27 mA, TX: 27
mA, microcontroller running at 32 MHz)
o Only 0.5 µA current consumption in powerdown
mode, where external interrupts or the RTC
can wake up the system
o 0.3 µA current consumption in stand-by mode,
where external interrupts can wake up the
system
o Very fast transition times from low-power
modes to active mode enables ultra low
average power consumption in low dutycycle
systems
o Wide supply voltage range (2.0V - 3.6V)
CC2430
®
combines the
CC2420
provides the market's
®
solution.
CC2430 Data Sheet (rev. 2.1) SWRS036F
• Low power wireless sensor networks
• PC peripherals
• Set-top boxes and remote controls
• Consumer Electronics
•
Microcontroller
o High performance and low power 8051
microcontroller core
o 32, 64 or 128 KB in-system programmable
flash
o 8 KB RAM, 4 KB with data retention in all
power modes
o Powerful DMA functionality
o Watchdog timer
o One IEEE 802.15.4 MAC timer, one general
16-bit timer and two 8-bit timers
o Hardware debug support
•
Peripherals
o CSMA/CA hardware support.
o Digital RSSI / LQI support
o Battery monitor and temperature sensor
o 12-bit ADC with up to eight inputs and
configurable resolution
o AES security coprocessor
o Two powerful USARTs with support for several
serial protocols
o 21 general I/O pins, two with 20mA sink/source
capability
•
Development tools
o Powerful and flexible development tools
available
CC2430
®
Page 1 of 211

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Summary of Contents for Texas Instruments Chipcon CC2430

  • Page 1 CC2430 A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee ® Applications • 2.4 GHz IEEE 802.15.4 systems • Low power wireless sensor networks ® • ZigBee • PC peripherals systems • Home/building automation • Set-top boxes and remote controls •...

  • Page 2: Table Of Contents

    CC2430 Table Of Contents ABBREVIATIONS..........................5 REFERENCES............................7 REGISTER CONVENTIONS ......................8 FEATURES EMPHASIZED ........................ 9 8051-C ....... 9 ERFORMANCE AND OWER OMPATIBLE ICROCONTROLLER 128 KB N 4 KB D ......9 P TO VOLATILE ROGRAM EMORY AND EMORY AES E ..................
  • Page 3 CC2430 13.1 P ....................65 OWER ANAGEMENT AND CLOCKS 13.2 R ..............................71 ESET 13.3 F ........................... 71 LASH ONTROLLER 13.4 I/O ............................77 PORTS 13.5 DMA C ..........................88 ONTROLLER 13.6 16- 1 ........................99 BIT TIMER IMER 13.7 MAC T 2)........................
  • Page 4 CC2430 18.5 C ..................207 ARRIER TAPE AND REEL SPECIFICATION ORDERING INFORMATION......................209 GENERAL INFORMATION ......................210 20.1 D ........................210 OCUMENT ISTORY ADDRESS INFORMATION ......................210 TI WORLDWIDE TECHNICAL SUPPORT ................. 210 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 4 of 211...

  • Page 5: Abbreviations

    CC2430 Abbreviations Analog to Digital Converter Input / Output Advanced Encryption Standard In-phase / Quadrature-phase Automatic Gain Control IEEE Institute of Electrical and Electronics Engineers ARIB Association of Radio Industries and Businesses Intermediate Frequency Binary Coded Decimal Integral Nonlinearity Bit Error Rate I/O Controller Brown Out Detector Interrupt Request...
  • Page 6 Tape and reel Pulse Width Modulator Transmit / Receive Quad Leadless Package To Be Decided / To Be Defined Random Access Memory Total Harmonic Distortion Resolution Bandwidth Texas Instruments Resistor-Capacitor Transmit RCOSC RC Oscillator UART Universal Asynchronous Receiver/Transmitter Radio Frequency...

  • Page 7: References

    CC2430 References IEEE std. 802.15.4 - 2003: Wireless Medium Access Control (MAC) and Physical Layer (PHY) specifications for Low Rate Wireless Personal Area Networks (LR-WPANs) http://standards.ieee.org/getieee802/download/802.15.4-2003.pdf NIST FIPS Pub 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/N.I.S.T., November 26, 2001. Available from the NIST website.

  • Page 8: Register Conventions

    CC2430 Register conventions Each SFR register is described in a separate REGISTER NAME (XDATA Address) table. The table heading is given in the In the register descriptions, each register bit is following format: shown with a symbol indicating the access REGISTER NAME (SFR Address) - Register mode of the register bit.

  • Page 9: Features Emphasized

    CC2430 Features Emphasized High-Performance Low-Power Low Power 8051-Compatible Microcontroller • Four flexible power modes for reduced • Optimized 8051 core, which typically power consumption gives 8x the performance of a standard • System can wake up on external 8051 interrupt or real-time counter event •...

  • Page 10: Absolute Maximum Ratings

    CC2430 Absolute Maximum Ratings Under no circumstances must the absolute maximum ratings given in Table 2 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Table 2: Absolute Maximum Ratings Parameter Units Condition Supply voltage...

  • Page 11: Electrical Specifications

    CC2430 Electrical Specifications CC2430 Measured on Texas Instruments EM reference design with T =25°C and VDD=3.0V unless stated otherwise. Table 4: Electrical Specifications Parameter Unit Condition Current Consumption Digital regulator on. 16 MHz RCOSC running. No radio, MCU Active Mode, 16 MHz, crystals, or peripherals active.

  • Page 12: General Characteristics

    CC2430 General Characteristics CC2430 Measured on Texas Instruments EM reference design with T =25°C and VDD=3.0V unless stated otherwise. Table 5: General Characteristics Parameter Unit Condition/Note Wake-Up and Timing Digital regulator on, 16 MHz RCOSC and Power mode 1 power µs...

  • Page 13: Rf Receive Section

    CC2430 RF Receive Section CC2430 Measured on Texas Instruments EM reference design with T =25°C and VDD=3.0V unless stated otherwise. Table 6: RF Receive Parameters Parameter Unit Condition/Note Receiver sensitivity PER = 1%, as specified by [1] Measured in 50 Ω single endedly through a balun.

  • Page 14: Mh Z Crystal Oscillator

    Differential impedance as seen from the RF-port ( RF_P impedance + j164 ) towards the antenna RF_N 32 MHz Crystal Oscillator CC2430 Measured on Texas Instruments EM reference design with T =25°C and VDD=3.0V unless stated otherwise. Table 8: 32 MHz Crystal Oscillator Parameters Parameter Unit Condition/Note...

  • Page 15: H Zrc Oscillator

    Simulated over operating conditions Simulated over operating conditions Start-up time Value is simulated. 32 kHz RC Oscillator CC2430 Measured on Texas Instruments EM reference design with T =25°C and VDD=3.0V unless stated otherwise. Table 10: 32 kHz RC Oscillator parameters Parameter...

  • Page 16: Frequency Synthesizer Characteristics

    Current consumption µA increase when enabled 7.10 ADC Measured with T =25°C and VDD=3.0V. Note that other data may result using Texas Instruments CC2430 EM reference design. Table 14: ADC Characteristics Parameter Unit Condition/Note...
  • Page 17 CC2430 Parameter Unit Condition/Note ENOB bits 7-bits setting. Single ended input 9-bits setting. 10-bits setting. 10.8 12-bits setting. ENOB bits 7-bits setting. Differential input 9-bits setting. 10.0 10-bits setting. 11.5 12-bits setting. Useful Power Bandwidth 0-20 7-bits setting, both single and differential -Single ended input -75.2 12-bits setting, -6dBFS...

  • Page 18: Control Ac Characteristics

    CC2430 7.11 Control AC Characteristics = -40°C to 85°C, VDD=2.0V to 3.6V if nothing else stated. Table 15: Control Inputs AC Characteristics Parameter Unit Condition/Note System clock, System clock is 32 MHz when crystal oscillator is used. System clock is 16 MHz when calibrated 16 MHz RC SYSCLK oscillator is used.

  • Page 19: Spi Ac Characteristics

    CC2430 7.12 SPI AC Characteristics = -40°C to 85°C, VDD=2.0V to 3.6V if nothing else stated. Table 16: SPI AC Characteristics Parameter Unit Condition/Note SCK period Master. See item 1 Figure 2 section 13.14.4 SCK duty cycle Master. SSN low to SCK See item 5 Figure 2 SYSCLK SCK to SSN high...

  • Page 20: Debug Interface Ac Characteristics

    CC2430 7.13 Debug Interface AC Characteristics = -40°C to 85°C, VDD=2.0V to 3.6V if nothing else stated. Table 17: Debug Interface AC Characteristics Parameter Unit Condition/Note Debug clock See item 1 Figure 3 period Debug data setup See item 2 Figure 3 Debug data hold See item 3 Figure 3 Clock to data...

  • Page 21: Port Outputs Ac Characteristics

    CC2430 7.14 Port Outputs AC Characteristics = 25°C, VDD=3.0V if nothing else stated. Table 18: Port Outputs AC Characteristics Parameter Unit Condition/Note Load = 10 pF P0_[0:7], P1_[2:7], 3.15/ Timing is with respect to 10% VDD and 90% VDD levels. P2_[0:4] Port output 1.34 rise time...

  • Page 22: Pin And I/O Port Configuration

    CC2430 Pin and I/O Port Configuration CC2430 pinout is shown in Figure 4 and Table 21. See section 13.4 for details on the configuration of digital I/O ports. Figure 4: Pinout top view Note: The exposed die attach pad must be connected to a solid ground plane as this is the ground connection for the chip.
  • Page 23 CC2430 Table 21: Pinout overview Pin name Pin type Description Ground The exposed die attach pad must be connected to a solid ground plane P1_7 Digital I/O Port 1.7 P1_6 Digital I/O Port 1.6 P1_5 Digital I/O Port 1.5 P1_4 Digital I/O Port 1.4 P1_3...

  • Page 24: Circuit Description

    CC2430 Circuit Description Figure 5: CC2430 Block Diagram CC2430 distribution, and radio-related modules. In the A block diagram of is shown in Figure following subsections, a short description of 5. The modules can be roughly divided into each module that appears in Figure 5 is given. one of three categories: CPU-related modules, modules related to power, test and clock CC2430 Data Sheet (rev.

  • Page 25: Cpu And Peripherals

    CC2430 CPU and Peripherals The 8051 CPU core is a single-cycle 8051- between single address compatible core. It has three different memory flash/SRAM. See section 13.5 for details. access buses (SFR, DATA The interrupt controller services a total of 18 CODE/XDATA), a debug interface and an 18- interrupt sources, divided into six interrupt input extended interrupt unit.

  • Page 26: Radio

    CC2430 capture the timing of edges on input signals. and hardware flow-control and are thus well See section 13.6 for details. suited high-throughput full-duplex applications. Each has its own high-precision MAC timer (Timer 2) is specially designed for baud-rate generator thus leaving the ordinary supporting an IEEE 802.15.4 MAC or other timers free for other uses.

  • Page 27: Application Circuit

    CC2430 10 Application Circuit Few external components are required for the description of external components are shown CC2430 in Table 23. operation of . A typical application circuit is shown in Figure 6. Typical values and 10.1 Input / output matching The RF input/output is high impedance and LNA (RX) and the PA (TX).

  • Page 28: Power Supply Decoupling And Filtering

    CC2430 10.6 Power supply decoupling and filtering Proper power supply decoupling must be used application. TI provides a compact reference for optimum performance. The placement and design that should be followed very closely. size of the decoupling capacitors and the Refer section Layout...
  • Page 29 CC2430 Table 23: Overview of external components (excluding supply decoupling capacitors) Component Description Differential Antenna Single Ended 50Ω Output C191 32 MHz crystal load capacitor 33 pF, 5%, NP0, 0402 33 pF, 5%, NP0, 0402 C211 32 MHz crystal load capacitor 27 pF, 5%, NP0, 0402 27 pF, 5%, NP0, 0402 C241...

  • Page 30: 8051 Cpu

    CC2430 8051 CPU : 8051 CPU Introduction 11 8051 CPU This section describes the 8051 CPU core, with interrupts, memory and instruction set. 11.1 8051 CPU Introduction CC2430 • includes an 8-bit CPU core which A second data pointer. • is an enhanced version of the industry Extended 18-source interrupt unit standard 8051 core.
  • Page 31 CC2430 8051 CPU : Memory Secondly, two alternative schemes for CODE The memory map showing how the different memory space mapping can be used. The first physical memories are mapped into the CPU scheme is the standard 8051 mapping where memory spaces is given in the figures on the only the program memory i.e.
  • Page 32 CC2430 8051 CPU : Memory 128 KB flash 0x1FFFF 32 KB bank 3 0x18000 0x17FFF 32 KB bank 2 0x10000 0x0FFFF 0xFFFF 0xFFFF Non-volatile program memory 32 KB 32 KB bank 1 bank 0 - bank 3 0x8000 0x08000 Code memory space 0x7FFF 0x07FFF Non-volatile program memory...
  • Page 33 CC2430 8051 CPU : Memory 11.2.2 CPU Memory Space This section describes the details of each CPU XDATA mapping. Note that some SFR memory space. registers internal to the CPU can not be accessed in the unified CODE memory space XDATA memory space.
  • Page 34 CC2430 8051 CPU : Memory specific SFR registers reside inside the CPU mapping into XDATA memory space. These core and can only be accessed using the SFR specific SFR registers are listed in section memory space and not through the duplicate 11.2.3, SFR registers, on page 34.
  • Page 35 CC2430 8051 CPU : Memory Table 24: SFR address overview 8 bytes DPL0 DPH0 DPL1 DPH1 U0CSR PCON TCON P0IFG P1IFG P2IFG PICTL P1IEN P0INP RFIM MPAGE T2CMP S0CON IEN2 S1CON T2PEROF0 T2PEROF1 T2PEROF2 FMAP T2OF0 T2OF1 T2OF2 T2CAPLPL T2CAPHPH T2TLD T2THD IEN0...
  • Page 36 CC2430 8051 CPU : Memory Register name Module Description Address P1IFG 0x8A Port 1 Interrupt Status Flag P2IFG 0x8B Port 2 Interrupt Status Flag PICTL 0x8C Port Pins Interrupt Mask and Edge P1IEN 0x8D Port 1 Interrupt Mask P0INP 0x8F Port 0 Input Mode PERCFG 0xF1...
  • Page 37 CC2430 8051 CPU : Memory Register name Module Description Address T2OF0 0xA1 Timer2 Timer 2 Overflow Count 0 T2OF1 0xA2 Timer2 Timer 2 Overflow Count 1 T2OF2 0xA3 Timer2 Timer 2 Overflow Count 2 T2CAPLPL 0xA4 Timer2 Timer 2 Timer Period Low T2CAPHPH 0xA5 Timer2...
  • Page 38 CC2430 8051 CPU : Memory Table 26: RFR address overview (XDATA addressable with offset DF00h) 8 bytes MDMCTRL0H MDMCTRL0L MDMCTRL1H MDMCTRL1L RSSIH RSSIL SYNCHWORDH SYNCWORDL TXCTRLH TXCTRLL RXCTRL0H RXCTRL0L RXCTRL1H RXCTRL1L FSCTRLH FSCTRLL CSPX CSPY CSPZ CSPCTRL CSPT RFPWR FSMTCH FSMTCL MANANDH MANANDL...
  • Page 39 CC2430 8051 CPU : Memory XDATA Register name Description Address 0xDF16 CSPT CSP T Data 0xDF17 RFPWR RF Power Control 0xDF20 FSMTCH Finite State Machine Time Constants, high 0xDF21 FSMTCL Finite State Machine Time Constants, low 0xDF22 MANANDH Manual AND Override, high 0xDF23 MANANDL Manual AND Override, low...
  • Page 40 CC2430 8051 CPU : Memory XDATA Register name Description Address 0xDF54 FSMTC1 Finite State Machine Control 0xDF55- Reserved 0xDF5F 0xDF60 CHVER Chip Version 0xDF61 CHIPID Chip Identification 0xDF62 RFSTATUS RF Status 0xDF63 Reserved 0xDF64 IRQSRC RF Interrupt Source 0xDF65- Reserved 0xDFFF 11.2.4 XDATA Memory Access...
  • Page 41 CC2430 8051 CPU : Memory MEMCTR (0xC7) – Memory Arbiter Control Name Reset Description Not used Unified memory mapping. When unified mapping is enabled, all MUNIF physical memories are mapped into the CODE memory space as far as possible, when uniform mapping is disabled only flash memory is mapped to CODE space Disable unified mapping Enable unified mapping...

  • Page 42: Cpu Registers

    CC2430 8051 CPU : CPU Registers 11.3 CPU Registers This section describes the internal registers found in the CPU. 11.3.1 Data Pointers CC2430 execution of an instruction that uses the data has two data pointers, DPTR0 pointer, e.g. in one of the above instructions. and DPTR1 to accelerate the movement of data blocks to/from memory.
  • Page 43 CC2430 8051 CPU : CPU Registers 11.3.3 Program Status Word The Program Status Word (PSW) contains Auxiliary Carry flag for BCD operations, several bits that show the current state of the Register Select bits, Overflow flag and Parity CPU. The Program Status Word is accessible flag.

  • Page 44: Instruction Set Summary

    CC2430 8051 CPU : Instruction Set Summary 11.3.6 Stack Pointer The stack resides in DATA memory space and which is the first register (R0) of the second grows upwards. The instruction first register bank. Thus, in order to use more than PUSH increments the Stack Pointer (SP) and then one register bank, the SP should be initialized...
  • Page 45 CC2430 8051 CPU : Instruction Set Summary Table 28: Instruction Set Summary Mnemonic Description Bytes Cycles Opcode Arithmetic operations ADD A,Rn Add register to accumulator 28-2F ADD A,direct Add direct byte to accumulator ADD A,@Ri Add indirect RAM to accumulator 26-27 ADD A,#data Add immediate data to accumulator...
  • Page 46 CC2430 8051 CPU : Instruction Set Summary Mnemonic Description Bytes Cycles Opcode Logical operations ANL A,Rn AND register to accumulator 58-5F ANL A,direct AND direct byte to accumulator ANL A,@Ri AND indirect RAM to accumulator 56-57 ANL A,#data AND immediate data to accumulator ANL direct,A AND accumulator to direct byte ANL direct,#data...
  • Page 47 CC2430 8051 CPU : Instruction Set Summary Mnemonic Description Bytes Cycles Opcode Data transfers MOV A,Rn Move register to accumulator E8-EF MOV A,direct Move direct byte to accumulator MOV A,@Ri Move indirect RAM to accumulator E6-E7 MOV A,#data Move immediate data to accumulator MOV Rn,A Move accumulator to register F8-FF...
  • Page 48 CC2430 8051 CPU : Instruction Set Summary Mnemonic Description Bytes Cycles Opcode Program branching ACALL addr11 Absolute subroutine call xxx11 LCALL addr16 Long subroutine call Return from subroutine RETI Return from interrupt AJMP addr11 Absolute jump xxx01 LJMP addr16 Long jump SJMP rel Short jump (relative address) JMP @A+DPTR...

  • Page 49: Interrupts

    CC2430 8051 CPU : Interrupts Table 29: Instructions that affect flag settings Instruction ADDC SUBB SETB C CLR C CPL C ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit MOV C,bit CJNE “0”=set to 0, “1”=set to 1, “x”=set to 0/1, “-“=not affected 11.5 Interrupts The CPU has 18 interrupt sources.
  • Page 50 CC2430 8051 CPU Interrupts interrupts missing this they are to be treated pulsed or edge shaped interrupt sources one as level triggered (apply to ports P0, P1 and should clear CPU interrupt flag registers prior P2). The switchboxes are shown in default to clearing source flag bit, if available, for flags that are not automatically cleared.
  • Page 51 CC2430 8051 CPU Interrupts Figure 10: CC2430 interrupt overview CC2430 revision E Data Sheet (rev. 2.1) SWRS036F Page 51 of 211...
  • Page 52 CC2430 8051 CPU Interrupts IEN0 (0xA8) – Interrupt Enable 0 Name Reset Description Disables all interrupts. No interrupt will be acknowledged Each interrupt source is individually enabled or disabled by setting its corresponding enable bit Not used. Read as 0 STIE –...
  • Page 53 CC2430 8051 CPU Interrupts IEN1 (0xB8) – Interrupt Enable 1 Name Reset Description Not used. Read as 0 P0IE – Port 0 interrupt enable P0IE Interrupt disabled Interrupt enabled T4IE - Timer 4 interrupt enable T4IE Interrupt disabled Interrupt enabled T3IE - Timer 3 interrupt enable T3IE Interrupt disabled...
  • Page 54 CC2430 8051 CPU Interrupts 11.5.2 Interrupt Processing When an interrupt occurs, the CPU will vector instruction cycle interrupt will to the interrupt vector address as shown in acknowledged by hardware forcing an LCALL Table 30. Once an interrupt service has to the appropriate vector address.
  • Page 55 CC2430 8051 CPU Interrupts S0CON (0x98) – Interrupt Flags 2 Name Reset Description 0x00 Not used ENCIF – AES interrupt. ENC has two interrupt flags, ENCIF_1 and ENCIF_1 ENCIF_0. Setting one of these flags will request interrupt service. Both flags are set when the AES co-processor requests the interrupt.
  • Page 56 CC2430 8051 CPU Interrupts IRCON (0xC0) – Interrupt Flags 4 Name Reset Description STIF – Sleep timer interrupt flag STIF Interrupt not pending Interrupt pending Must be written 0. Writing a 1 will always enable interrupt source. P0IF – Port 0 interrupt flag P0IF Interrupt not pending Interrupt pending...
  • Page 57 CC2430 8051 CPU Interrupts IRCON2 (0xE8) – Interrupt Flags 5 Name Reset Description Not used WDTIF – Watchdog timer interrupt flag. WDTIF Interrupt not pending Interrupt pending P1IF – Port 1 interrupt flag. P1IF Interrupt not pending Interrupt pending UTX1IF – USART1 TX interrupt flag. UTX1IF Interrupt not pending Interrupt pending...
  • Page 58 CC2430 8051 CPU Interrupts IP0 (0xA9) – Interrupt Priority 0 Name Reset Description Not used. Interrupt group 5, priority control bit 0, refer to Table 32: Interrupt IP0_IPG5 Priority Groups Interrupt group 4, priority control bit 0, refer to Table 32: Interrupt IP0_IPG4 Priority Groups Interrupt group 3, priority control bit 0, refer to Table 32: Interrupt...
  • Page 59 CC2430 8051 CPU Interrupts Table 33: Interrupt Polling Sequence Interrupt number Interrupt name RFERR Polling sequence URX0 URX1 P0INT P2INT UTX0 UTX1 P1INT CC2430 Data Sheet (rev. 2.1) SWRS036F Page 59 of 211...

  • Page 60: Debug Interface

    CC2430 Debug Interface Debug Mode 12 Debug Interface CC2430 The debug interface uses the I/O pins P2_1 as includes a debug interface that Debug Data and P2_2 as Debug Clock during provides a two-wire interface to an on-chip Debug mode. These I/O pins can be used as debug module.
  • Page 61 CC2430 Debug Interface Debug Lock Bit Note that after the Debug Lock bit has the Debug Interface needs to select the Flash changed due to a flash information page write Information Page first instead of the Flash or a flash mass erase, a HALT, RESUME, Main Pages which is the default setting.
  • Page 62 CC2430 Debug Interface Debug Lock Bit Table 35: Debug Commands Command Instruction code Description CHIP_ERASE 0001 0000 Perform flash chip erase (mass erase) and clear lock bits. If any other command, except READ_STATUS, is issued, then the use of CHIP_ERASE is disabled. WR_CONFIG 0001 1001 Write configuration data.
  • Page 63 CC2430 Debug Interface Debug Lock Bit Table 36: Debug Configuration Name Description Not used, must be set to zero. Disable timers. Disable timer operation. This overrides the TIMERS_OFF TIMER_SUSPEND bit and its function. 0 Do not disable timers 1 Disable timers DMA pause DMA_PAUSE 0 Enable DMA transfers...
  • Page 64 CC2430 Debug Interface Debug interface and Power Modes The first data byte consists of the following: The second data byte consists of bits 15-8 of the hardware breakpoint. • bits 7-5 : unused The third data byte consists of bits 7-0 of the •...

  • Page 65: Debug Interface And Power Modes Peripherals

    CC2430 Peripherals Power Management and clocks 13 Peripherals CC2430 In the following sub-sections each peripheral described detail. 13.1 Power Management and clocks This section describes Power power modes and clock control to achieve low- Management Controller. Power power operation. Management Controller controls the use of 13.1.1 Power Management Introduction CC2430...
  • Page 66 CC2430 Peripherals Power Management and clocks 13.1.1.2 In PM1, the high-frequency oscillators are will run on the 16MHz RC oscillator until powered down (32MHz XOSC and 16MHz RC 32MHz is selected as source by SW. OSC). The voltage regulator and the enabled PM1 is used when the expected time until a 32 kHz oscillator is on.
  • Page 67 CC2430 Peripherals Power Management and clocks PCON (0x87) – Power Mode Control Name Reset Description 0x00 Not used. Not used, always read as 0. CC2430 R0/W Power mode control. Writing a 1 to this bit forces to enter IDLE the power mode set by (note that = 0x00 SLEEP.MODE...
  • Page 68 CC2430 Peripherals Power Management and clocks Figure 12: Clock System Overview 13.1.4 Oscillators and clocks CC2430 There is also one 32 kHz clock source that can has one internal system clock. either be a RC oscillator or a crystal oscillator, The source for the system clock can be either a 16 MHz RC oscillator or a 32 MHz crystal also controlled by the CLKCON register.
  • Page 69 CC2430 Peripherals Power Management and clocks • The 32 kHz crystal oscillator is designed to 32 MHz crystal oscillator. • operate at 32.768 kHz and provide a stable 16 MHz RC oscillator. clock signal for systems requiring time The 32 MHz crystal oscillator startup time may accuracy.
  • Page 70 CC2430 Peripherals Power Management and clocks therefore the calibration may be disabled by completed when written setting register bit SLEEP.OSC32K_CALDIS SLEEP.OSC32K_CALDIS. to 1. Note that any ongoing calibration will be 13.1.4.4 Oscillator and Clock Registers This section describes the Oscillator and Clock values when entering PM2 or PM3 unless registers.

  • Page 71: Reset

    CC2430 Peripherals Reset 0xFEFF (426 bytes) will lose all data when transparent to software with the following PM2 or PM3 is entered. These locations will exceptions: contain undefined data when PM0 is re- • The RF TXFIFO/RXFIFO contents are not entered.
  • Page 72 CC2430 Peripherals Flash Controller The Flash Controller handles writing and • Lock bits for write-protection and code erasing the embedded flash memory. The security embedded flash memory consists of 64 pages • Flash page erase timing 20 ms of 2048 bytes each (CC2430F128). •...
  • Page 73 CC2430 Peripherals Flash Controller 13.3.2.1 DMA Flash Write When using DMA write operations, the data to When the DMA channel is armed, starting a be written into flash is stored in the XDATA flash write by setting FCTL.WRITE to 1 will memory space (RAM or FLASH).
  • Page 74 CC2430 Peripherals Flash Controller Setup DMA channel: SRCADDR=<XDATA location> DESTADDRR=FWDATA VLEN=0 LEN=<block size> WORDSIZE=byte TMODE=single mode TRIG=FLASH SRCINC=yes DESTINC=no IRQMASK=yes M8=0 PRIORITY=high Setup flash address Arm DMA Channel Start flash write Figure 15: Flash write using DMA 13.3.2.2 CPU Flash Write The CPU can also write directly to the flash after FCTL.WRITE set for first time write.
  • Page 75 CC2430 Peripherals Flash Controller Figure 16: Performing CPU Flash write 13.3.3 Flash Page Erase After a flash page erase, all bytes in the Performing flash erase from flash memory erased page are set to 1. The steps required to perform a flash page page erase initiated...
  • Page 76 CC2430 Peripherals Flash Controller 13.3.4 Flash Write Timing Flash Controller contains timing The value set in the FWT.FWT[5:0] shall be generator, which controls the timing sequence set according to the CPU clock frequency. The of flash write and erase operations. The timing initial value held in FWT.FWT[5:0] after a generator uses the information set in the Flash reset is 0x2A which corresponds to 32 MHz...

  • Page 77: I/Oports

    CC2430 Peripherals I/O ports FCTL (0xAE) – Flash Control Name Reset Description Indicates that write or erase is in operation BUSY No write or erase operation active Write or erase operation activated Indicates that current word write is busy; avoid writing to FWDATA SWBSY register while this is true Ready to accept data...
  • Page 78 CC2430 Peripherals I/O ports • The external interrupt capability is available on 21 digital input/output pins • all 21 I/O pins. Thus external devices may General purpose I/O or peripheral I/O generate interrupts if required. The external • Pull-up or pull-down capability on inputs interrupt feature can also be used to wake up •...
  • Page 79 CC2430 Peripherals I/O ports nibble have their individual interrupt enables. cleared prior to clearing the CPU port interrupt For the P2_0 – P2_4 inputs there is a common flag (PxIF). interrupt enable. The I/O SFR registers used for interrupts are When an interrupt condition occurs on one of described in section 13.4.9 on page 82.
  • Page 80 CC2430 Peripherals I/O ports Table 40: Peripheral I/O Pin Mapping Periphery / Function USART0 SPI Alt. 2 USART0 UART Alt. 2 USART1 SPI Alt. 2 USART1 UART Alt. 2 TIMER1 Alt. 2 TIMER3 Alt. 2 TIMER4 Alt. 2 32.768 kHz XOSC DEBUG 13.4.6.1...
  • Page 81 CC2430 Peripherals I/O ports 13.4.6.4 USART0 The SFR register bit PERCFG.U0CFG selects selects order P2DIR.PRIP0 whether to use alternative 1 or alternative 2 precedence when assigning several locations. peripherals to port 0. When set to 00, USART0 has precedence. Note that if UART mode is In Table 40, the USART0 signals are shown as selected and hardware flow control is disabled, follows:...
  • Page 82 CC2430 Peripherals I/O ports 13.4.8 32.768 kHz XOSC input Ports P2_3 and P2_4 are used to connect an regardless of register settings. The port pins external 32.768 kHz crystal. These port pins will analog mode when will be used by the 32.768 kHz crystal CLKCON.OSC32K is low.
  • Page 83 CC2430 Peripherals I/O ports P2 (0xA0) – Port 2 Name Reset Description Not used 0x1F Port 2. General purpose I/O port. Bit-addressable. P2[4:0] PERCFG (0xF1) – Peripheral Control Name Reset Description Not used Timer 1 I/O location T1CFG Alternative 1 location Alternative 2 location Timer 3 I/O location T3CFG...
  • Page 84 CC2430 Peripherals I/O ports P2SEL (0xF5) – Port 2 Function Select Name Reset Description Not used Port 1 peripheral priority control. These bits shall determine which PRI3P1 module has priority in the case when modules are assigned to the same pins. USART0 has priority USART1 has priority Port 1 peripheral priority control.
  • Page 85 CC2430 Peripherals I/O ports P2DIR (0xFF) – Port 2 Direction Name Reset Description Port 0 peripheral priority control. These bits shall determine the PRIP0[1:0] order of priority in the case when PERCFG assigns several peripherals to the same pins USART0 has priority over USART1 USART1 has priority OVER Timer1 Timer 1 channels 0 and 1has priority over USART1 Timer 1 channel 2 has priority over USART0...
  • Page 86 CC2430 Peripherals I/O ports P0IFG (0x89) – Port 0 Interrupt Status Flag Name Reset Description 0x00 R/W0 Port 0, inputs 7 to 0 interrupt status flags. When an input port pin P0IF[7:0] has an interrupt request pending, the corresponding flag bit will be set.
  • Page 87 CC2430 Peripherals I/O ports PICTL (0x8C) – Port Interrupt Control Name Reset Description Not used Drive strength control for I/O pins in output mode. Selects output PADSC drive capability to account for low I/O supply voltage on pin DVDD (this to ensure same drive strength at lower voltages as is on higher).

  • Page 88: Dma Controller

    CC2430 Peripherals DMA Controller 13.5 DMA Controller CC2430 periodically transfer samples between ADC includes a direct memory access and memory, etc. Use of the DMA can also (DMA) controller, which can be used to relieve reduce system power consumption by keeping 8051 core handling...
  • Page 89 CC2430 Peripherals DMA Controller Figure 18: DMA Operation 13.5.2 DMA Configuration Parameters Setup and control of the DMA operation is The behavior of each of the five DMA channels performed by the user software. This section is configured with the following parameters: describes the parameters which must be Source address: The first address from which configured before a DMA channel can be...
  • Page 90 CC2430 Peripherals DMA Controller read from the source address. The user must Source and Destination Increment: The ensure that the destination is writable. source and destination addresses can be controlled to increment or decrement or not Transfer count: The number of transfers to change.
  • Page 91 CC2430 Peripherals DMA Controller 4. Transfer number bytes/words Figure 19 shows the VLEN options. commanded first byte/word (transfers the length byte/word, and then as many bytes/words as dictated by length byte/word + 2) byte/word n+2 byte/word n+1 byte/word n+1 byte/word n byte/word n byte/word n byte/word n-1...
  • Page 92 CC2430 Peripherals DMA Controller 13.5.2.8 DMA Priority A DMA priority is configurable for each DMA High: Highest internal priority. DMA access channel. priority used will always prevail over CPU access. determine the winner in the case of multiple Normal: Second highest internal priority. This simultaneous internal memory requests, and guarantees that DMA access prevails over whether the DMA memory access should have...
  • Page 93 CC2430 Peripherals DMA Controller 13.5.5 DMA Interrupts Each DMA channel can be configured to Regardless of the IRQMASK bit in the channel generate an interrupt to the CPU upon configuration, the interrupt flag will be set upon completing transfer. This DMA channel complete.
  • Page 94 CC2430 Peripherals DMA Controller Table 41: DMA Trigger Sources DMA Trigger Functional unit Description Trigger name number NONE No trigger, setting bit starts transfer DMAREQ.DMAREQx PREV DMA channel is triggered by completion of previous channel T1_CH0 Timer 1, compare, channel 0 Timer 1 T1_CH1 Timer 1, compare, channel 1...
  • Page 95 CC2430 Peripherals DMA Controller Table 42: DMA Configuration Data Structure Byte Name Description Offset The DMA channel source address, high SRCADDR[15:8] The DMA channel source address, low SRCADDR[7:0] The DMA channel destination address, high. Note that flash memory is not directly DESTADDR[15:8] writeable.
  • Page 96 CC2430 Peripherals DMA Controller Byte Name Description Offset Mode of 8 bit for VLEN transfer length; only applicable when WORDSIZE=0. 0 : Use all 8 bits for transfer count 1 : Use 7 LSB for transfer count The DMA channel priority: PRIORITY[1:0] 00 : Low, CPU has priority.
  • Page 97 CC2430 Peripherals DMA Controller DMAREQ (0xD7) – DMA Channel Start Request and Status Name Reset Description Not used DMA transfer request, channel 4 DMAREQ4 R/W1 When set to 1 activate the DMA channel (has the same effect as a single trigger event.). Only by setting the armed bit to 0 in the register, can the channel be DMAARM...
  • Page 98 CC2430 Peripherals DMA Controller DMA1CFGL (0xD2) – DMA Channel 1-4 Configuration Address Low Byte Name Reset Description The DMA channel 1-4 configuration address, low order DMA1CFG[7:0] 0x00 DMAIRQ (0xD1) – DMA Interrupt Flag Name Reset Description Not used R/W0 DMA channel 4 interrupt flag. DMAIF4 R/W0 0 : DMA channel transfer not complete...

  • Page 99: 16-Bit Timer, Timer1

    CC2430 Peripherals 16-bit timer, Timer1 13.6 16-bit timer, Timer1 • Timer 1 is an independent 16-bit timer which Three capture/compare channels supports typical timer/counter functions such • Rising, falling or any edge input capture as input capture, output compare and PWM •...
  • Page 100 CC2430 Peripherals 16-bit timer, Timer1 FFFFh 0000h OVFL OVFL Figure 20: Free-running mode 13.6.4 Modulo Mode When the timer operates in modulo mode the count value is reached. An interrupt request is 16-bit counter starts at 0x0000 and increments generated if the corresponding interrupt mask at each active clock edge.
  • Page 101 CC2430 Peripherals 16-bit timer, Timer1 T1CC0 0000h OVFL OVFL Figure 22 : Up/down mode 13.6.6 Channel Mode Control The channel mode is set with each channel’s settings include input capture and output compare modes. control and status register T1CCTLn. The 13.6.7 Input Capture Mode When a channel is configured as an input...
  • Page 102 CC2430 Peripherals 16-bit timer, Timer1 when the counter reaches 0x0000 instead of PWM signal is determined by T1CC0 and the when a compare occurs. duty cycle for the channel output is determined by T1CCn, where n is the PWM channel 1 or 2. Examples of output compare modes in various timer modes are given in the following figures.
  • Page 103 CC2430 Peripherals 16-bit timer, Timer1 FFFFh T1CC0 T1CCn 0000h 0 - Set output on compare 1 - Clear output on compare 2 - Toggle output on compare 3 - Set output on compare-up, clear on 0 4 - Clear output on compare-up, set on 0 5 - Clear when T1CC0, set when T1CCn 6 - Set when T1CC0, clear when T1CCn...
  • Page 104 CC2430 Peripherals 16-bit timer, Timer1 T1CC0 0000h 0 - Set output on compare 1 - Clear output on compare 2 - Toggle output on compare 3 - Set output on compare-up, clear on 0 4 - Clear output on compare-up, set on 0 5 - Clear when T1CC0, set when T1CCn 6 - Set when T1CC0, clear when T1CCn...
  • Page 105 CC2430 Peripherals 16-bit timer, Timer1 T 1 C C 0 T 1 C C n 00 00 h 0 - S et ou tp ut on com pa re 1 - C le ar ou tp ut on com p are 2 - T og gle ou tpu t on co m pa re 3 - S et ou tp ut on com p are -u p , clea r o n co m pa re -d ow n...
  • Page 106 CC2430 Peripherals 16-bit timer, Timer1 13.6.11 Timer 1 Registers This section describes the Timer 1 registers • T1CCxL – Timer 1 Channel x which consist of the following registers: Capture/Compare Value Low • T1CNTH – Timer 1 Count High The TIMIF.OVFIM register bit resides in the •...
  • Page 107 CC2430 Peripherals 16-bit timer, Timer1 T1CCTL0 (0xE5) – Timer 1 Channel 0 Capture/Compare Control Name Reset Description Reserved. Always set to 0 Channel 0 interrupt mask. Enables interrupt request when set. Channel 0 compare mode select. Selects action on output when CMP[2:0] timer value equals compare value in T1CC0...
  • Page 108 CC2430 Peripherals 16-bit timer, Timer1 T1CCTL1 (0xE6) – Timer 1 Channel 1 Capture/Compare Control Name Reset Description Reserved. Always set to 0. Channel 1 interrupt mask. Enables interrupt request when set. Channel 1 compare mode select. Selects action on output when CMP[2:0] timer value equals compare value in T1CC1...
  • Page 109 CC2430 Peripherals 16-bit timer, Timer1 T1CCTL2 (0xE7) – Timer 1 Channel 2 Capture/Compare Control Name Reset Description Reserved. Always set to 0. Channel 2 interrupt mask. Enables interrupt request when set. Channel 2 compare mode select. Selects action on output when CMP[2:0] timer value equals compare value in T1CC2...

  • Page 110: Mac Timer (Timer2)

    CC2430 Peripherals MAC Timer (Timer2) 13.7 MAC Timer (Timer2) • The MAC Timer is mainly used to provide 8-bit timer compare function timing for 802.15.4 CSMA-CA algorithms and • 20-bit overflow count for general timekeeping in the 802.15.4 MAC • 20-bit overflow count compare function layer.
  • Page 111 CC2430 Peripherals MAC Timer (Timer2) the timer is to be compared is set by the request is also generated if the interrupt mask T2CNF.CMSEL bit. T2PEROF2.CMPIM is set to 1. When a timer compare occurs the interrupt flag T2CNF.CMPIF is set to 1. An interrupt 13.7.1.6 Capture Input The MAC timer has a timer capture function...
  • Page 112 CC2430 Peripherals MAC Timer (Timer2) 13.7.4.1 General The Timer can be started and stopped At the time of a synchronous start the timer is synchronously with the 32kHz clock rising reloaded with new calculated values for the edge. Note this event is derived from a 32kHz timer and overflow count such that it appears clock signal, but is synchronous with the that the timer has not been stopped (e.g.
  • Page 113 CC2430 Peripherals MAC Timer (Timer2) when using Timer2 in PM1 or PM2. T2CAPHPH and T2CAPHPL should be avoided 13.7.5 Timer 2 Registers The SFR registers associated with Timer 2 are • T2OF0 – Timer 2 Overflow Count 0 listed in this section. These registers are the •...
  • Page 114 CC2430 Peripherals MAC Timer (Timer2) T2THD (0xA7) – Timer 2 Timer Value High Byte Name Reset Description The value read from this register is the high-order byte of the timer THD[7:0] 0x00 value. The high-order byte read is from timer value at the last instant when was read.
  • Page 115 CC2430 Peripherals MAC Timer (Timer2) T2OF0 (0xA1) – Timer 2 Overflow Count 0 Name Reset Description OF0[7:0] Overflow count. Low bits T2OF[7:0]. T2OF is incremented by 1 each 0x00 time the timer overflows i.e. timer counts to a value greater or equal to period.
  • Page 116 CC2430 Peripherals MAC Timer (Timer2) T2PEROF0 (0x9C) – Timer 2 Overflow Capture/Compare 0 Name Reset Description PEROF0[7:0] Overflow count capture /Overflow count compare value. Writing these 0x00 bits set the low bits [7:0] of the overflow count compare value. Reading these bits returns the low bits [7:0] of the overflow count value at the time of the last capture event.

  • Page 117: 8- Bit Timers , Timer 3 And Timer 4

    CC2430 Peripherals 8-bit timers, Timer 3 and Timer 4 13.8 8-bit timers, Timer 3 and Timer 4 • Timer 3 and 4 are two 8-bit timers which Two compare channels support typical timer/counter functions souch • Set, clear or toggle output compare as output compare and PWM functions.
  • Page 118 CC2430 Peripherals 8-bit timers, Timer 3 and Timer 4 13.8.3 Channel Mode Control The channel modes for each channel; 0 and 1, TxCCTLn where n is the channel number, 0 or are set by the control and status registers 1. The settings include output compare modes. 13.8.4 Output Compare Mode In output compare mode the I/O pin associated...
  • Page 119 CC2430 Peripherals 8-bit timers, Timer 3 and Timer 4 T3CTL (0xCB) – Timer 3 Control Name Reset Description Prescaler divider value. Generates the active clock edge used to DIV[2:0] clock the timer from as follows: CLKCON.TICKSPD Tick frequency /1 Tick frequency /2 Tick frequency /4 Tick frequency /8 Tick frequency /16...
  • Page 120 CC2430 Peripherals 8-bit timers, Timer 3 and Timer 4 T3CCTL0 (0xCC) – Timer 3 Channel 0 Compare Control Name Reset Description Unused Channel 0 interrupt mask 0 : interrupt is disabled 1 : interrupt is enabled Channel 0 compare output mode select. Specified action on output CMP[2:0] when timer value equals compare value in T3CC0...
  • Page 121 CC2430 Peripherals 8-bit timers, Timer 3 and Timer 4 T3CCTL1 (0xCE) – Timer 3 Channel 1 Compare Control Name Reset Description Unused Channel 1 interrupt mask 0 : interrupt is disabled 1 : interrupt is enabled Channel 1 compare output mode select. Specified action on output CMP[2:0] when timer value equals compare value in T3CC1...
  • Page 122 CC2430 Peripherals 8-bit timers, Timer 3 and Timer 4 T4CTL (0xEB) – Timer 4 Control Name Reset Description Prescaler divider value. Generates the active clock edge used to DIV[2:0] clock the timer from as follows: CLKCON.TICKSPD Tick frequency /1 Tick frequency /2 Tick frequency /4 Tick frequency /8 Tick frequency /16...
  • Page 123 CC2430 Peripherals 8-bit timers, Timer 3 and Timer 4 T4CCTL0 (0xEC) – Timer 4 Channel 0 Compare Control Name Reset Description Unused Channel 0 interrupt mask Channel 0 compare output mode select. Specified action on output CMP[2:0] when timer value equals compare value in T4CC0 Set output on compare Clear output on compare...
  • Page 124 CC2430 Peripherals 8-bit timers, Timer 3 and Timer 4 T4CCTL1 (0xEE) – Timer 4 Channel 1 Compare Control Name Reset Description Unused Channel 1 interrupt mask Channel 1 compare output mode select. Specified action on output CMP[2:0] when timer value equals compare value in T4CC1 Set output on compare Clear output on compare...
  • Page 125 CC2430 Peripherals 8-bit timers, Timer 3 and Timer 4 TIMIF (0xD8) – Timers 1/3/4 Interrupt Mask/Flag Name Reset Description Unused Timer 1 overflow interrupt mask OVFIM R/W0 Timer 4 channel 1 interrupt flag T4CH1IF 0 : no interrupt is pending 1 : interrupt is pending R/W0 Timer 4 channel 0 interrupt flag...

  • Page 126: Sleep Timer

    CC2430 Peripherals Sleep Timer 13.9 Sleep Timer The Sleep timer is used to set the period The main features of the Sleep timer are the between when the system enters and exits following: low-power sleep modes. • 24-bit timer up-counter operating at 32kHz The Sleep timer is also used to maintain timing clock in Timer 2 (MAC Timer) when entering a low-...
  • Page 127 CC2430 Peripherals Sleep Timer ST0 (0x95) – Sleep Timer 0 Name Reset Description ST0[7:0] Sleep timer count/compare value. When read, this register returns the 0x00 low bits [7:0] of the sleep timer count. When writing this register sets the low bits [7:0] of the compare value. CC2430 Data Sheet (rev.

  • Page 128: Adc

    CC2430 Peripherals 13.10 ADC 13.10.1 ADC Introduction • The ADC supports up to 12-bit analog-to- Eight individual input channels, single- digital conversion. The ADC includes an ended or differential analog multiplexer with up to eight individually • Reference voltage selectable as internal, configurable channels, reference...
  • Page 129 CC2430 Peripherals It is also possible to select a voltage this feature is required. Alle these input corresponding to AVDD_SOC/3 as an ADC configurations are controlled by the register input. This input allows the implementation of ADCCON2.SCH e.g. a battery monitor in applications where 13.10.2.3 ADC conversion sequences The ADC can perform a sequence of...
  • Page 130 CC2430 Peripherals where Vinn=0V). The maximum value is 1. Note that the conversion result always reached when the input amplitude is equal resides in MSB section of combined ADCH VREF, the selected voltage reference. For and ADCL registers. differential configurations difference When the ADCCON2.SCH bits are read, they between two pin pairs are converted and this...
  • Page 131 CC2430 Peripherals ADCH (0xBB) – ADC Data High Name Reset Description 0x00 Most significant part of ADC conversion result. ADC[13:6] ADCCON1 (0xB4) – ADC Control 1 Name Reset Description End of conversion Cleared when ADCH has been read. If a new conversion is completed before the previous data has been read, the EOC bit will remain high.
  • Page 132 CC2430 Peripherals ADCCON2 (0xB5) – ADC Control 2 Name Reset Description Selects reference voltage used for the sequence of conversions SREF[1:0] Internal 1.25V reference External reference on AIN7 pin AVDD_SOC pin External reference on AIN6-AIN7 differential input Sets the decimation rate for channels included in the sequence of SDIV[1:0] conversions.
  • Page 133 CC2430 Peripherals ADCCON3 (0xB6) – ADC Control 3 Name Reset Description Selects reference voltage used for the extra conversion EREF[1:0] Internal 1.25V reference External reference on AIN7 pin AVDD_SOC pin External reference on AIN6-AIN7 differential input Sets the decimation rate used for the extra conversion. The EDIV[1:0] decimation rate also determines the resolution and time required to complete the conversion.

  • Page 134: Random Number Generator

    CC2430 Peripherals Random Number Generator 13.11 Random Number Generator 13.11.1 Introduction The random number generator has the The random number generator is a 16-bit following features. Linear Feedback Shift Register (LFSR) with polynomial (i.e. CRC16). • Generate pseudo-random bytes which can It uses different levels of unrolling depending be read by the CPU or used directly by the on the operation it performs.
  • Page 135 CC2430 Peripherals Random Number Generator 13.11.3 Random Number Generator Registers This section describes the Random Number Generator registers. RNDL (0xBC) – Random Number Generator Data Low Byte Name Reset Description [7:0] 0xFF Random value/seed or CRC result, low byte RNDL[7:0] When used for random number generation writing this register twice will seed the random number generator.

  • Page 136: Aes Coprocessor

    CC2430 Peripherals AES Coprocessor 13.12 AES Coprocessor CC2430 • data encryption is performed using Supports all security suites in IEEE a dedicated coprocessor which supports the 802.15.4 Advanced Encryption Standard, AES. The • ECB, CBC, CFB, OFB, CTR and CBC- coprocessor allows encryption/decryption to be MAC modes.
  • Page 137 CC2430 Peripherals AES Coprocessor be changed to CBC. The last block is then CCM is a combination of CBC-MAC and CTR. downloaded and the block uploaded will be the Parts of the CCM must therefore be done in MAC value. software.
  • Page 138 CC2430 Peripherals AES Coprocessor unchanged, while setting the lower bits to 0 (M must be zero. When encrypting message != 16). blocks using CTR mode, CTR value must be any value but zero. The result is called T. The content of the Encryption Flag byte is Message Encryption described in Figure 31.
  • Page 139 CC2430 Peripherals AES Coprocessor (7) The software calls a CTR mode decryption is that the result is named MACTag (instead of right now on the encrypted message blocks C. It does not have to reload the IV/CTR. Message Authentication checking Phase Reference Authentication tag generation The software compares T with MACTag.
  • Page 140 CC2430 Peripherals AES Coprocessor ENCCS (0xB3) – Encryption Control and Status Name Reset Description Not used, always read as 0 Encryption/decryption mode MODE[2:0] CBC MAC Not used Not used Encryption/decryption ready status Encryption/decryption in progress Encryption/decryption is completed Command to be performed when a 1 is written to CMD[1:0] encrypt block decrypt block...

  • Page 141: Watchdog Timer

    CC2430 Peripherals Watchdog Timer 13.13 Watchdog Timer • The watchdog timer (WDT) is intended as a Four selectable timer intervals recovery method in situations where the CPU • Watchdog mode may be subjected to a software upset. The • Timer mode WDT shall reset the system when software •...
  • Page 142 CC2430 Peripherals Watchdog Timer counting will start from zero. In PM1 the immediately after waking up from PM1. watchdog is still running, but it will not reset the sleep timer and the watchdog run on the the chip while in PM1. This will not happen same clock the watchdog timeout interval can until it is woken up (it will wrap around and be aligned with sleep timer interval so SW can...

  • Page 143: Usart

    CC2430 Peripherals USART 13.14 USART USART0 USART1 serial two USARTs have identical function, and are communications interfaces that assigned to separate I/O pins. Refer to section operated separately in either asynchronous 13.1 for I/O configuration. UART mode or in synchronous SPI mode. The 13.14.1 UART mode For asynchronous serial interfaces, the UART...
  • Page 144 CC2430 Peripherals USART The receiver will check both stop bits when in when the framing error bit, UxCSR.FE, is UxUCR.SPB is set. Note that the RX interrupt set. This delay is baud rate dependable (bit will be set when first stop bit is checked OK. If duration).
  • Page 145 CC2430 Peripherals USART At the end of the transfer, the received data The transmit interrupt is generated at the start byte is available for reading from UxDBUF of the operation. 13.14.3 SSN Slave Select Pin When the USART is operating in SPI mode, released in a byte the next received byte will configured as an SPI slave, a 4-wire interface not be received properly as information about...
  • Page 146 CC2430 Peripherals USART 13.14.5 USART flushing The current operation can be aborted by timer keeping knowledge of bit duration will not). Thus using the flush bit should either be setting the UxUCR.FLUSH register bit. This aligned with USART interrupts or use a wait event will stop the current operation and clear time of one bit duration at current baud rate all data buffers.
  • Page 147 CC2430 Peripherals USART U0CSR (0x86) – USART 0 Control and Status Name Reset Description MODE USART mode select SPI mode UART mode UART receiver enable Receiver disabled Receiver enabled SLAVE SPI master or slave mode select SPI master SPI slave R/W0 UART framing error status No framing error detected...
  • Page 148 CC2430 Peripherals USART U0UCR (0xC4) – USART 0 UART Control Name Reset Description R0/W1 Flush unit. When set, this event will stop the current operation and FLUSH return the unit to idle state. UART hardware flow enable. Selects use of hardware flow control FLOW with RTS and CTS pins Flow control disabled...
  • Page 149 CC2430 Peripherals USART U0GCR (0xC5) – USART 0 Generic Control Name Reset Description SPI clock polarity CPOL Negative clock polarity Positive clock polarity SPI clock phase CPHA Data is output on MOSI when SCK goes from CPOL inverted to CPOL, and data input is sampled on MISO when SCK goes from CPOL to CPOL inverted.
  • Page 150 CC2430 Peripherals USART U1CSR (0xF8) – USART 1 Control and Status Name Reset Description MODE USART mode select SPI mode UART mode UART receiver enable Receiver disabled Receiver enabled SLAVE SPI master or slave mode select SPI master SPI slave R/W0 UART framing error status No framing error detected...
  • Page 151 CC2430 Peripherals USART U1UCR (0xFB) – USART 1 UART Control Name Reset Description R0/W1 Flush unit. When set, this event will immediately stop the current FLUSH operation and return the unit to idle state. UART hardware flow enable. Selects use of hardware flow control FLOW with RTS and CTS pins Flow control disabled...
  • Page 152 CC2430 Peripherals USART U1GCR (0xFC) – USART 1 Generic Control Name Reset Description SPI clock polarity CPOL Negative clock polarity Positive clock polarity SPI clock phase CPHA Data is output on MOSI when SCK goes from CPOL inverted to CPOL, and data input is sampled on MISO when SCK goes from CPOL to CPOL inverted.

  • Page 153: Radio

    CC2430 Radio USART 14 Radio AUTOMATIC GAIN CONTROL DIGITAL RADIO DEMODULATOR REGISTER Register bus - Digital RSSI BANK - Gain Control - Image Suppression - Channel Filtering FFCTRL - Demodulation - Frame synchronization CSMA/CA STROBE TXRX SWITCH PROCESSOR FREQ SYNTH SFR bus TX POWER CONTROL DIGITAL...

  • Page 154: Ieee 802.15.4 Modulation Format

    CC2430 Radio IEEE 802.15.4 Modulation Format 14.1 IEEE 802.15.4 Modulation Format This section is meant as an introduction to the For multi-byte fields, the least significant byte 2.4 GHz direct sequence spread spectrum is transmitted first. (DSSS) RF modulation format defined in IEEE Each symbol is mapped to one out of 16 802.15.4.

  • Page 155: Command Strobes

    CC2430 Radio Command strobes I-phase Q-phase Figure 34: I / Q Phases when transmitting a zero-symbol chip sequence, T = 0.5 µs 14.2 Command strobes The CPU uses a set of command strobes to individually to the radio or they can be given in CC2430 a sequence together with a set of dedicated control operation of the radio in...
  • Page 156 CC2430 Radio Interrupts processing this type of interrupt as described The interrupt flags in SFR register RFIF show below. the status for each interrupt source for the RF interrupt vector. To clear the RF interrupt, S1CON.RFIF and The interrupt enable bits in RFIM are used to the interrupt flag in RFIF need to be cleared.

  • Page 157: Fifo Access

    CC2430 Radio FIFO access RFIM (0x91) – RF Interrupt Mask Name Reset Description Voltage regulator for radio has been turned on IM_RREG_PD Interrupt disabled Interrupt enabled TX completed with packet sent. Also for acknowledge frames if RF IM_TXDONE register IRQSRC.TXACK is 1 Interrupt disabled Interrupt enabled Number of bytes in RXFIFO is above threshold set by...

  • Page 158: Receive Mode

    CC2430 Radio Receive mode event that causes a RADIO DMA trigger, is RFD SFR register) and there is still more data when data is read from the RXFIFO (through available in the RXFIFO. 14.7 Receive mode receive mode, interrupt flag number of bytes in the RXFIFO exceeds the programmed threshold.

  • Page 159: Transmit Mode

    CC2430 Radio Transmit mode Data received over RF Preamble SFD Length MAC Protocol Data Unit (MPDU) with correct address Address recognition OK FIFO FIFOP , if threshold higher than frame length FIFOP , if threshold lower than frame length Data received over RF Preamble SFD Length MAC Protocol Data Unit (MPDU) with wrong address...

  • Page 160: General Control And Status

    CC2430 Radio General control and status Data Lengt transmitted Preamble MAC Protocol Data Unit (MPDU) over RF 12 symbol periods Automatically generated Data fetched generated preamble and SFD from TXFIFO Figure 37: SFD status activity example during transmit 14.10 General control and status In receive mode, the RFIF.IRQ_FIFOP For debug purposes, the RFSTATUS.SFD, interrupt flag and RF interrupt request can be...

  • Page 161: Frame Format

    CC2430 Radio Frame Format Digital Frequency Digital Symbol Data I / Q Analog IF Channel Offset Data Correlators and Symbol IF signal Filtering Compensation Filtering Synchronisation Output Average RSSI Correlation RSSI Value (may be Generator used for LQI) Figure 38: Demodulator Simplified Block Diagram 14.12 Frame Format CC2430 Figure 39 [1] shows a schematic view of the...

  • Page 162: Length Field

    CC2430 Radio Length field CC2430 used for byte synchronization, and is not part In receive mode uses the preamble of the data stored in the receive buffer sequence for symbol synchronization and (RXFIFO). frequency offset adjustments. The SFD is Synchronisation Header Preamble IEEE 802.15.4 2·(PREAMBLE_LENGTH + 1) zero symbols...

  • Page 163: Rf Data Buffering

    CC2430 Radio RF Data Buffering CC2430 and CRC OK/not OK. This is illustrated in hardware implementation is Figure 43. shown in Figure 42. Please refer to [1] for further details. The first FCS byte is replaced by the 8-bit RSSI value. See the RSSI section on page In transmit mode the FCS is appended at the 168 for details.

  • Page 164: Address Recognition

    CC2430 Radio Address Recognition has been transmitted, data is fetched from the STXONCCA command strobe will then cause TXFIFO. CC2430 to retransmit the last frame. The TXFIFO can only contain one data frame Writing to the TXFIFO after a frame has been at a given time.

  • Page 165: Acknowledge Frames

    CC2430 Radio Acknowledge Frames these frames. This option is included for future The MDMCTRL0.PAN_COORDINATOR control expansions of the IEEE 802.15.4 standard. bit must be correctly set, since parts of the address recognition procedure requires CC2430 If a frame is rejected, will only start knowledge about whether the current device is searching for a new frame after the rejected...

  • Page 166: Radio Control State Machine

    CC2430 Radio Radio control state machine SLOTTED_ACK = 0 PPDU Acknowledge = 12 sym bol periods SLOTTED_ACK = 1 = 20 sym bol periods backoffslot PPDU Acknowledge = 12 - 30 sym bol periods Figure 45: Acknowledge frame timing 14.20 Radio control state machine CC2430 SLEEP.XOSC_STB bit indicates whether the has a built-in state machine that is...
  • Page 167 CC2430 Radio Radio control state machine Figure 46: Radio control states CC2430 Data Sheet (rev. 2.1) SWRS036F Page 167 of 211...

  • Page 168: Mac Security Operations (Encryption And Authentication)

    CC2430 Radio MAC Security Operations (Encryption and Authentication) 14.21 MAC Security Operations (Encryption and Authentication) CC2430 features hardware IEEE 802.15.4 MAC security operations. Refer to section 13.12 on page 136 for a description of the AES encryption unit. 14.22 Linear IF and AGC Settings C2430 dynamic range by using an analog/digital is based on a linear IF chain where the...

  • Page 169: Clear Channel Assessment

    CC2430 Radio Clear Channel Assessment therefore also provides an average correlation quality frame while a value of approx. 50 is value for each incoming packet, based on the typically the lowest quality frames detectable CC2430 eight first symbols following the SFD. This unsigned 7-bit value, which should be as high Software must convert the correlation value to as possible, can be looked upon as a...

  • Page 170: Output Power Programming

    CC2430 Radio Output Power Programming 14.27.1 The VCO is completely integrated and frequencies in the desired band (2400-2483.5 operates at 4800 – 4966 MHz. The VCO MHz). frequency is divided by 2 to generate 14.27.2 PLL self-calibration The VCO's characteristics will vary with mode or TX mode is enabled, i.e.

  • Page 171: Transmitter Test Modes

    CC2430 Radio Transmitter Test Modes 14.30 Transmitter Test Modes CC2430 can be set into different transmit test oscillator is selected using the CLKCON modes for performance evaluation. The test register and that the crystal oscillator has mode descriptions in the following sections stabilized.
  • Page 172 CC2430 Radio Transmitter Test Modes pseudorandom bit sequence for bit error Another option to generate a modulated CC2430 spectrum is to fill the TXFIFO with pseudo- testing. Please note that requires symbol synchronization, only random data and set MDMCTRL1L.TX_MODE to CC2430 synchronization, for correct reception.

  • Page 173: System Considerations And Guidelines

    CC2430 Radio System Considerations and Guidelines 14.31 System Considerations and Guidelines 14.31.1 SRD regulations International regulations and national laws important regulations are ETSI EN 300 328 regulate the use of radio receivers and and EN 300 440 (Europe), FCC CFR-47 part transmitters.
  • Page 174 CC2430 Radio System Considerations and Guidelines CC2430 of data processing, which is costly in an 8-bit within enables a high level of security microcontroller system. The hardware support with minimum CPU processing requirements. 14.31.7 Low cost systems CC2430 A differential antenna will eliminate the need As the provides 250 kbps multi- for a balun, and the DC biasing can be...

  • Page 175: Pcb Layout Recommendation

    Table 44 on 14.32 PCB Layout Recommendation In the Texas Instruments reference design, the The external components should be as small top layer is used for signal routing, and the as possible (0402 is recommended) and open areas are filled with metallization surface mount devices must be used.

  • Page 176: Csma/Ca Strobe Processor

    CC2430 Radio CSMA/CA Strobe Processor The antenna should be connected as close as matched to the feeding transmission line possible to the IC. If the antenna is located (50Ω). away from the RF pins the antenna should be 14.34 CSMA/CA Strobe Processor The Command Strobe/CSMA-CA Processor Strobe instruction is also used only to control (CSP) provides the control interface between...
  • Page 177 CC2430 Radio CSMA/CA Strobe Processor 14.34.2 Data Registers decremented by 1 each time the MAC timer The CSP has three data registers CSPT, CSPX, overflows. When CSPT reaches zero, program which read/write CSPY CSPZ, execution halted interrupt accessible for the CPU as RF registers. These IRQ_CSP_STOP is asserted.
  • Page 178 CC2430 Radio CSMA/CA Strobe Processor Write instruction to RFST All instructions written? Setup CSPT, CSPX, CSPY, CSPZ and CSPCTRL registers Start execution by writing ISSTART to RFST SSTOP instruction, end of program or writing ISTOP to RFST stops program Figure 50: Running a CSP program 14.34.7 Instruction Set Summary This section gives an overview of the...
  • Page 179 CC2430 Radio CSMA/CA Strobe Processor Table 46: Instruction Set Summary Opcode Bit number Mnemonic Description Skip S instructions when condition (C xor SKIP C,S N) is true. See Table 48 for C conditional codes Wait for W number of MAC Timer WAIT W overflows.
  • Page 180 CC2430 Radio CSMA/CA Strobe Processor Table 47: CSMA/CA strobe processor instruction details NMONIC OPCODE Function Operation Description Decrement Z The Z register is decremented by 1. Original values of 0x00 will underflow to 0x0FF. DECZ 0xBF Z := Z - 1 Decrement Y The Y register is decremented by 1.
  • Page 181 CC2430 Radio CSMA/CA Strobe Processor NMONIC OPCODE Function Operation Description The SSTOP instruction stops the CSP program execution. The instruction memory is Stop program execution cleared, any loop start location set by the LABEL instruction is invalidated and the STOP 0xDF Stop exec, PC:=0, write pointer:=0 IRQ_CSP_STOP interrupt flag is asserted.
  • Page 182 CC2430 Radio CSMA/CA Strobe Processor NMONIC OPCODE Function Operation Description The ISRXON instruction immediately enables and calibrates frequency synthesizer for Enable and calibrate freq. RX. The instruction waits for the radio to acknowledge the command before executing ISRXON 0xE2 SRXON synth.

  • Page 183: Radio Registers

    CC2430 Radio Radio Registers Table 48: Condition code for C Condition Description Function code C CCA is true CCA = 1 Transmiting or Receiving packet SFD = 1 CPU control true CSPCTRL.CPU_CTRL=1 End of instruction memory PC = 23 Register X=0 X = 0 Register Y=0 Y = 0...
  • Page 184 CC2430 Radio Radio Registers XDATA Register name Description Address 0xDF20 FSMTCH Finite State Machine Time Constants, high 0xDF21 FSMTCL Finite State Machine Time Constants, low 0xDF22 MANANDH Manual AND Override, high 0xDF23 MANANDL Manual AND Override, low 0xDF24 MANORH Manual OR Override, high 0xDF25 MANORL Manual OR Override, low...
  • Page 185 CC2430 Radio Radio Registers XDATA Register name Description Address 0xDF54 FSMTC1 Finite State Machine Control 0xDF55- Reserved 0xDF5F 0xDF60 CHVER Chip Version 0xDF61 CHIPID Chip Identification 0xDF62 RFSTATUS RF Status 0xDF63 Reserved 0xDF64 IRQSRC RF Interrupt Source The RF registers shown in Table 50 are reserved for test purposes. The values for these registers ®...
  • Page 186 CC2430 Radio Radio Registers MDMCTRL0H (0xDF02) Name Reset Function These bits are used to perform special operations on the FRAMET_FILT frame type field of a received packet. These operations do not influence the packet that is written to the RXFIFO. 00 : Leave frame type as it is.
  • Page 187 CC2430 Radio Radio Registers MDMCTRL0L (0xDF03) Name Reset Description Clear Channel Assessment mode select. CCA_MODE[1:0] 00 : Reserved 01 : CCA=1 when RSSI < CCA_THR-CCA_HYST CCA=0 when RSSI >= CCA_THR 10 : CCA=1 when not receiving a packet 11 : CCA=1 when RSSI < CCA_THR-CCA_HYST and not receiving a packet CCA=0 when RSSI >= CCA_THR or receiving a packet In packet mode a CRC-16 (ITU-T) is calculated and is...
  • Page 188 CC2430 Radio Radio Registers MDMCTRL1L (0xDF05) Name Reset Description Reserved, read as 0. DC average filter behavior. DEMOD_AVG_MODE 0 : Lock DC level to be removed after preamble match 1 : Continuously update DC average level. Set one of two RF modulation modes for RX / TX MODULATION_MODE 0 : IEEE 802.15.4 compliant mode 1 : Reversed phase, non-IEEE compliant (could be used to...
  • Page 189 CC2430 Radio Radio Registers RSSIL (0xDF07) Name Reset Description RSSI estimate on a logarithmic scale, signed number in 2’s RSSI_VAL[7:0] 0x80 complement. Unit is 1 dB, offset is TBD [depends on the absolute gain of the RX chain, including external components, and should be measured].
  • Page 190 CC2430 Radio Radio Registers TXCTRLL (0xDF0B) Name Reset Description Current programming of the PA PA_CURRENT[2:0] 000 : -3 current adjustment 001 : -2 current adjustment 010 : -1 current adjustment 011 : Nominal setting 100 : +1 current adjustment 101 : +2 current adjustment 110 : +3 current adjustment 111 : +4 current adjustment Output PA level.
  • Page 191 CC2430 Radio Radio Registers RXCTRL1H (0xDF0E) Name Reset Description Reserved, read as 0. Controls reference bias current to RX band-pass filters: RXBPF_LOCUR 0 : 4 uA 1 : 3 uA (Default) Controls reference bias current to RX band-pass filters: RXBPF_MIDCUR 0 : 4 uA (Default) 1 : 3.5 uA LNA low gain mode setting in AGC low gain mode.
  • Page 192 CC2430 Radio Radio Registers FSCTRLH (0xDF10) Name Reset Description Number of consecutive reference clock periods with LOCK_THR[1:0] successful sync windows required to indicate lock: 00 : 64 01 : 128 10 : 256 11 : 512 Frequency synthesizer calibration done. CAL_DONE 0 : Calibration not performed since the last time the FS was turned on.
  • Page 193 CC2430 Radio Radio Registers CSPY (0xDF13) Name Reset Description CSP Y Data register. Used by CSP INCY, DECY, CSPY 0x00 INCMAXY, RANDXY and conditional instructions CSPZ (0xDF14) Name Reset Description CSP Z Data register. Used by CSP DECZ and conditional CSPZ 0x00 instructions...
  • Page 194 CC2430 Radio Radio Registers FSMTCH (0xDF20) Name Reset Description The time in 5 us steps between the time the RX chain is TC_RXCHAIN2RX[2:0] enabled and the demodulator and AGC is enabled. The RX chain is started when the band pass filter has been calibrated (after 6.5 symbol periods).
  • Page 195 CC2430 Radio Radio Registers MANANDL (0xDF23) Name Reset Description Reserved, read as 0 Powerdown control of complex band pass receive filter RXBPF_CAL_PD calibration oscillator. Powerdown control of charge pump. CHP_PD Powerdown control of VCO, I/Q generator, LO buffers. FS_PD Powerdown control of the ADCs. ADC_PD Powerdown control of the VGA.
  • Page 196 CC2430 Radio Radio Registers AGCCTRLH (0xDF26) Name Reset Description Use the VGA_GAIN value during RX instead of the AGC VGA_GAIN_OE value. When written, VGA manual gain override value; when read, VGA_GAIN[6:0] 0x7F the currently used VGA gain setting. AGCCTRLL (0xDF27) Name Reset Description...
  • Page 197 CC2430 Radio Radio Registers DACTSTH (0xDF3C) Name Reset Description Reserved, read as 0. The TX DACs data source is selected by DAC_SRC DAC_SRC[2:0] according to: 000 : Normal operation (from modulator). 001 : The DAC_I_O and DAC_Q_O override values below.- 010 : From ADC, most significant bits 011 : I/Q after digital down mix and channel filtering.
  • Page 198 CC2430 Radio Radio Registers IEEE_ADDR5 (0xDF48) Name Reset Description IEEE ADDR byte 5 IEEE_ADDR5[7:0] 0x00 IEEE_ADDR6 (0xDF49) Name Reset Description IEEE ADDR byte 6 IEEE_ADDR6[7:0] 0x00 IEEE_ADDR7 (0xDF4A) Name Reset Description IEEE ADDR byte 7 (MSB) IEEE_ADDR7[7:0] 0x00 PANIDH (0xDF4B) Name Reset Description...
  • Page 199 CC2430 Radio Radio Registers IOCFG1 (0xDF50) Name Reset Description Reserved, read as 0. CCA is output on P1.7 when this bit is 1 OE_CCA Polarity of the IO_CCA signal. This bit is xor’ed with the IO_CCA_POL internal CCA signal. Multiplexer setting for the CCA signal. Must be 0x00 in IO_CCA_SEL 00000 order to output the CCA status.
  • Page 200 CC2430 Radio Radio Registers FSMTC1 (0xDF54) Name Reset Description Reserved, read as 0. Abort RX when SRXON strobe is issued ABORTRX_ON_SRXON 0 : Packet reception is not aborted when SRXON is issued 1 : Packet reception is aborted when SRXON is issued RX interrupted by strobe command RX_INTERRUPTED This bit is cleared when the next strobe is detected.
  • Page 201 CC2430 Radio Radio Registers RFSTATUS (0xDF62) Name Reset Description Reserved, read as 0. TX active indicates transmission in progress TX_ACTIVE 0 : TX inactive 1 : TX active RXFIFO data available FIFO 0 : No data available in RXFIFO 1 : One or more bytes available in RXFIFO RXFIFO threshold flag FIFOP 0 : Number of bytes in RXFIFO is less or equal threshold...

  • Page 202: Voltage Regulators

    ® ® Windows NT/2000/XP. SmartRF Studio can with a software program, SmartRF Studio, be downloaded from the Texas Instruments which may be used for radio performance and ® web page: http://www.ti.com/lpw functionality evaluation. SmartRF Studio runs CC2430 Data Sheet (rev. 2.1) SWRS036F...

  • Page 203: Register Overview

    CC2430 17 Register overview ACC (0xE0) – Accumulator ........................43 ADCCFG (0xF2) – ADC Input Configuration ..................83 ADCCON1 (0xB4) – ADC Control 1....................131 ADCCON2 (0xB5) – ADC Control 2....................132 ADCCON3 (0xB6) – ADC Control 3....................133 ADCH (0xBB) – ADC Data High ......................131 ADCL (0xBA) –...
  • Page 204 CC2430 IOCFG2 (0xDF51)..........................199 IOCFG3 (0xDF52)..........................199 IP0 (0xA9) – Interrupt Priority 0 ......................58 IP1 (0xB9) – Interrupt Priority 1 ......................57 IRCON (0xC0) – Interrupt Flags 4 ......................56 IRCON2 (0xE8) – Interrupt Flags 5....................... 57 IRQSRC (0xDF64) ..........................201 MANANDH (0xDF22) ..........................194 MANANDL (0xDF23)...........................195 MANORH (0xDF24) ..........................195 MANORL (0xDF25)..........................195...
  • Page 205 CC2430 ST2 (0x97) – Sleep Timer 2 ........................126 SYNCWORDH (0xDF08) ........................189 SYNCWORDL (0xDF09)........................189 T1CC0H (0xDB) – Timer 1 Channel 0 Capture/Compare Value High..........107 T1CC0L (0xDA) – Timer 1 Channel 0 Capture/Compare Value Low ..........107 T1CC1H (0xDD) – Timer 1 Channel 1 Capture/Compare Value High ..........108 T1CC1L (0xDC) –...

  • Page 206: Package Description (Qlp 48)

    CC2430 18 Package Description (QLP 48) CC2430 All dimensions are in millimeters, angles in degrees. NOTE: The is available in RoHS lead- free package only. Compliant with JEDEC MS-020. Table 51: Package dimensions Quad Leadless Package (QLP) QLP 48 6.65 6.65 0.18 5.05...

  • Page 207: Recommended Pcb Layout For Package (Qlp 48)

    CC2430 18.1 Recommended PCB layout for package (QLP 48) Figure 52: Recommended PCB layout for QLP 48 package Note: The figure is an illustration only and not to scale. There are nine 14 mil diameter via holes CC2430 distributed symmetrically in the ground pad under the package. See also the EM reference design 18.2 Package thermal properties...
  • Page 208 CC2430 Table 54: Carrier tape and reel specification Tape and Reel Specification Package Tape Width Component Hole Reel Units per Reel Pitch Pitch Diameter QLP 48 16mm 12mm 13 inches 2500 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 208 of 211...

  • Page 209: Ordering Information

    CC2430 19 Ordering Information Table 55: Ordering Information Ordering part Description number CC2430F128RTC CC2430, QLP48 package, RoHS compliant Pb-free assembly, trays with 260 pcs per tray, 128 Kbytes in-system programmable flash memory, System-on-chip RF transceiver. CC2430F128RTCR CC2430, QLP48 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per 2,500 reel, 128 Kbytes in-system programmable flash memory, System-on-chip RF transceiver.

  • Page 210: General Information

    Preliminary data sheets exist for engineering samples and pre-production prototype devices, but these data sheets are not complete and may be incorrect in some aspects compared with the released product. 21 Address Information Texas Instruments Norway AS Gaustadalléen 21 N-0349 Oslo NORWAY...
  • Page 211 CC2430 Japan International +81-3-3344-5317 Domestic 0120-81-0036 International support.ti.com/sc/pic/japan.htm Internet/Email Domestic www.tij.co.jp/pic Asia International +886-2-23786800 Phone Domestic Toll-Free Number Australia 1-800-999-084 China 800-820-8682 Hong Kon 800-96-5941 India +91-80-51381665 (Toll) Indonesia 001-803-8861-1006 Korea 080-551-2804 Malaysia 1-800-80-3973 New Zealand 0800-446-934 Philippines 1-800-765-7404 Singapore 800-886-1028 Taiwan 0800-006800...
  • Page 212 PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) CC2430F32RTCR VQFN 2500 330.0 16.4 12.0 16.0 CC2430F64RTCR VQFN 2500...
  • Page 213 PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2010 *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) CC2430F32RTCR VQFN 2500 333.2 345.9 28.6 CC2430F64RTCR VQFN 2500 378.0 70.0 346.0 CC2430ZF128RTCR VQFN 2500 378.0 70.0 346.0 Pack Materials-Page 2...
  • Page 214 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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