Debug Command Interface Schematic; Debug Command Interface Pins - Motorola M68060 User Manual

9.2.1 Debug Command Interface
Figure 9-10 illustrates the debug command interface and Table 9-4 outlines the pins needed
by the debug command interface. The debug command interface consists of a five-bit shift
register and a five-bit parallel register, with each register operating independently. To acti-
vate the debug command interface, JTAG must be driven negated. This allows the debug
command interface to take over the regular JTAG interface and remap JTAG pin functions.
The resulting interface is fully synchronous to the CLK input.
TRST (PDISABLE)
TDI (PTDI)
TCK (PSHIFT)
TDO (PTDO)
TMS (PAPPLY)
Figure 9-10. Debug Command Interface Schematic
The commands enter the debug command interface through the PTDI serial input signal into
the five-bit shift register. The shift register is controlled by the PSHIFT input. The PSHIFT
signal determines which rising CLK edge contains valid data on the PTDI input. When
asserted the PSHIFT input causes data from the PTDI input to be latched and causes inter-
nal data bits already in the shift register to be passed on to the next shift register bit. Serial
data eventually shifts out through the PTDO output. PTDO can be used as a status output
and can be used to verify that the shift register is operating properly. Do not assert both PAP-
PLY and PSHIFT on the same CLK edge as this is interpreted as a "no operation".
MOTOROLA
D31–D0
A31–A0
CLK
JTAG
CONTROLLER
R
MC68060 CHIP BOUNDARY
Table 9-4. Debug Command Interface Pins
Pin Name Alias
TCK PSHIFT
TMS PAPPLY
TDI PTDI
TRST PDISABLE
TDO PTDO
JTAG JTAG
CLK CLK
M68060 USER'S MANUAL
IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
TO ALL
FLIP-FLOPS
COMMAND
VALID
BIT 4
P
S
A
E
R
5-BIT
A
COMMAND
I
L
WORD
A
L
L
E
L
BIT 0
Description
Serial Shift Enable
Command Apply Enable
Serial Command Data In
Debug Command Disable
Serial Command Data Out
JTAG or Debug Select
Clock
OEP
CONTROL LOGIC
9-25